[PATCH] D148316: [AArch64] Add support for efficient bitcast in vector truncate store.

[Lawrence Benson via Phabricator via llvm-commits]

lawben added a comment.

I dug into this a bit, and your vector compare sing bit patch <https://reviews.llvm.org/D148624> does the right thing here. But the problem is unrelated and a bit annoying. At the time the `sign_extend_inreg` that we added is combined (to potentially remove it), there is a `build_vector` with `(1 << vectorElementSize) - 1` bits (to negate via `xor`). But `ComputeNumSignBits` breaks here. The vector has 32-bit constants but we only have 8-bit vectors. So it detects 24 sign bits and then kinda gives up. So without changing code in `SelectionDAG::ComputeNumSignBits` or the negation of vector entries, there is no way to correctly determine the sign bits.

If you have any ideas how to overcome this, please let me know. Otherwise, I'd leave this in `performSTORECombine` to apply it before legalization (`vec != 0` --> `(vec == 0) ^ 255` ) breaks it.


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https://reviews.llvm.org/D148316