[PATCH] D148316: [AArch64] Add support for efficient bitcast in vector truncate store.

Lawrence Benson via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Apr 19 01:29:45 PDT 2023


lawben added a comment.

In D148316#4277254 <https://reviews.llvm.org/D148316#4277254>, @dmgreen wrote:

> Does having sign bits for the vector compare nodes help, as in https://reviews.llvm.org/D148624? I wasn't able to find a good way to test that, the optimizer would always clear away the results for all the examples I tried prior to creating the compare nodes.

Unfortunately, it does not. I'll try to dig into this tomorrow when I have some time. I'm not familiar with how the sign extend is removed but if we have the new method in `lowerSTORE`, there is an `xor` with a 0-vector, which I'm not sure passes the known sign bits check. I'll let you know once I have some more insights from digging into it. Maybe I can get this to work,


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https://reviews.llvm.org/D148316



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