[PATCH] D147713: [RISCV] Combine concat_vectors of loads into strided loads

[Luke Lau via Phabricator via llvm-commits]

luke added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:11475-11477
+    if (!allowsMemoryAccessForAlignment(*DAG.getContext(), DAG.getDataLayout(),
+                                        WideVecVT, *MMO))
+      break;
----------------
Is it legal to increase the alignment here?
E.g. for these loads

```
%0 = load <4 x i8>, ptr %pix1, align 1
%add.ptr = getelementptr inbounds i8, ptr %pix1, i64 %idx.ext
%2 = load <4 x i8>, ptr %add.ptr, align 1
```

Can we use an align of 4 * 1:

```
%0 = call <2 x i32> @llvm.riscv.strided.load ptr %pix1, i64 %idx.ext, align 4
```



Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147713/new/

https://reviews.llvm.org/D147713