[llvm] 51892a4 - [COFF][ARM] Fix CodeView for Windows on 32bit ARM targets.
Luqman Aden via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 19 22:17:10 PDT 2020
Author: Luqman Aden
Date: 2020-10-19T22:16:16-07:00
New Revision: 51892a42dac55558f7dbec80ced570e72ff387c4
URL: https://github.com/llvm/llvm-project/commit/51892a42dac55558f7dbec80ced570e72ff387c4
DIFF: https://github.com/llvm/llvm-project/commit/51892a42dac55558f7dbec80ced570e72ff387c4.diff
LOG: [COFF][ARM] Fix CodeView for Windows on 32bit ARM targets.
Create the LLVM / CodeView register mappings for the 32-bit ARM Window targets.
Reviewed By: compnerd
Differential Revision: https://reviews.llvm.org/D89622
Added:
llvm/test/DebugInfo/COFF/ARMNT/arm-register-variables.ll
llvm/test/DebugInfo/COFF/ARMNT/lit.local.cfg
Modified:
llvm/include/llvm/DebugInfo/CodeView/CodeViewRegisters.def
llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
llvm/lib/DebugInfo/CodeView/EnumTables.cpp
llvm/lib/DebugInfo/PDB/PDBExtras.cpp
llvm/lib/ObjectYAML/CodeViewYAMLSymbols.cpp
llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
llvm/tools/llvm-pdbutil/MinimalSymbolDumper.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/DebugInfo/CodeView/CodeViewRegisters.def b/llvm/include/llvm/DebugInfo/CodeView/CodeViewRegisters.def
index ed5c143818e6..48ea7e52c172 100644
--- a/llvm/include/llvm/DebugInfo/CodeView/CodeViewRegisters.def
+++ b/llvm/include/llvm/DebugInfo/CodeView/CodeViewRegisters.def
@@ -15,6 +15,7 @@
#endif
#if !defined(CV_REGISTERS_ALL) && !defined(CV_REGISTERS_X86) && \
+ !defined(CV_REGISTERS_ARM) && \
!defined(CV_REGISTERS_ARM64)
#error Need include at least one register set.
#endif
@@ -393,13 +394,46 @@ CV_REGISTER(ARM_PC, 25)
// Status register
-CV_REGISTER(ARM_CPSR, 25)
+CV_REGISTER(ARM_CPSR, 26)
// ARM VFPv1 registers
CV_REGISTER(ARM_FPSCR, 40)
CV_REGISTER(ARM_FPEXC, 41)
+CV_REGISTER(ARM_FS0, 50)
+CV_REGISTER(ARM_FS1, 51)
+CV_REGISTER(ARM_FS2, 52)
+CV_REGISTER(ARM_FS3, 53)
+CV_REGISTER(ARM_FS4, 54)
+CV_REGISTER(ARM_FS5, 55)
+CV_REGISTER(ARM_FS6, 56)
+CV_REGISTER(ARM_FS7, 57)
+CV_REGISTER(ARM_FS8, 58)
+CV_REGISTER(ARM_FS9, 59)
+CV_REGISTER(ARM_FS10, 60)
+CV_REGISTER(ARM_FS11, 61)
+CV_REGISTER(ARM_FS12, 62)
+CV_REGISTER(ARM_FS13, 63)
+CV_REGISTER(ARM_FS14, 64)
+CV_REGISTER(ARM_FS15, 65)
+CV_REGISTER(ARM_FS16, 66)
+CV_REGISTER(ARM_FS17, 67)
+CV_REGISTER(ARM_FS18, 68)
+CV_REGISTER(ARM_FS19, 69)
+CV_REGISTER(ARM_FS20, 70)
+CV_REGISTER(ARM_FS21, 71)
+CV_REGISTER(ARM_FS22, 72)
+CV_REGISTER(ARM_FS23, 73)
+CV_REGISTER(ARM_FS24, 74)
+CV_REGISTER(ARM_FS25, 75)
+CV_REGISTER(ARM_FS26, 76)
+CV_REGISTER(ARM_FS27, 77)
+CV_REGISTER(ARM_FS28, 78)
+CV_REGISTER(ARM_FS29, 79)
+CV_REGISTER(ARM_FS30, 80)
+CV_REGISTER(ARM_FS31, 81)
+
// ARM VFPv3/NEON registers
CV_REGISTER(ARM_FS32, 200)
diff --git a/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
index bcace6264cd0..98fccf009338 100644
--- a/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
@@ -126,7 +126,9 @@ static CPUType mapArchToCVCPUType(Triple::ArchType Type) {
case Triple::ArchType::x86_64:
return CPUType::X64;
case Triple::ArchType::thumb:
- return CPUType::Thumb;
+ // LLVM currently doesn't support Windows CE and so thumb
+ // here is indiscriminately mapped to ARMNT specifically.
+ return CPUType::ARMNT;
case Triple::ArchType::aarch64:
return CPUType::ARM64;
default:
diff --git a/llvm/lib/DebugInfo/CodeView/EnumTables.cpp b/llvm/lib/DebugInfo/CodeView/EnumTables.cpp
index 82f6713a88f5..949707bf5475 100644
--- a/llvm/lib/DebugInfo/CodeView/EnumTables.cpp
+++ b/llvm/lib/DebugInfo/CodeView/EnumTables.cpp
@@ -39,6 +39,14 @@ static const EnumEntry<uint16_t> RegisterNames_X86[] = {
#undef CV_REGISTERS_X86
};
+static const EnumEntry<uint16_t> RegisterNames_ARM[] = {
+#define CV_REGISTERS_ARM
+#define CV_REGISTER(name, val) CV_ENUM_CLASS_ENT(RegisterId, name),
+#include "llvm/DebugInfo/CodeView/CodeViewRegisters.def"
+#undef CV_REGISTER
+#undef CV_REGISTERS_ARM
+};
+
static const EnumEntry<uint16_t> RegisterNames_ARM64[] = {
#define CV_REGISTERS_ARM64
#define CV_REGISTER(name, val) CV_ENUM_CLASS_ENT(RegisterId, name),
@@ -434,7 +442,9 @@ ArrayRef<EnumEntry<TypeLeafKind>> getTypeLeafNames() {
}
ArrayRef<EnumEntry<uint16_t>> getRegisterNames(CPUType Cpu) {
- if (Cpu == CPUType::ARM64) {
+ if (Cpu == CPUType::ARMNT) {
+ return makeArrayRef(RegisterNames_ARM);
+ } else if (Cpu == CPUType::ARM64) {
return makeArrayRef(RegisterNames_ARM64);
}
return makeArrayRef(RegisterNames_X86);
diff --git a/llvm/lib/DebugInfo/PDB/PDBExtras.cpp b/llvm/lib/DebugInfo/PDB/PDBExtras.cpp
index 354a99476c4b..25962e5152eb 100644
--- a/llvm/lib/DebugInfo/PDB/PDBExtras.cpp
+++ b/llvm/lib/DebugInfo/PDB/PDBExtras.cpp
@@ -118,7 +118,21 @@ raw_ostream &llvm::pdb::operator<<(raw_ostream &OS, const PDB_DataKind &Data) {
raw_ostream &llvm::pdb::operator<<(raw_ostream &OS,
const llvm::codeview::CPURegister &CpuReg) {
- if (CpuReg.Cpu == llvm::codeview::CPUType::ARM64) {
+ if (CpuReg.Cpu == llvm::codeview::CPUType::ARMNT) {
+ switch (CpuReg.Reg) {
+#define CV_REGISTERS_ARM
+#define CV_REGISTER(name, val) \
+ case codeview::RegisterId::name: \
+ OS << #name; \
+ return OS;
+#include "llvm/DebugInfo/CodeView/CodeViewRegisters.def"
+#undef CV_REGISTER
+#undef CV_REGISTERS_ARM
+
+ default:
+ break;
+ }
+ } else if (CpuReg.Cpu == llvm::codeview::CPUType::ARM64) {
switch (CpuReg.Reg) {
#define CV_REGISTERS_ARM64
#define CV_REGISTER(name, val) \
diff --git a/llvm/lib/ObjectYAML/CodeViewYAMLSymbols.cpp b/llvm/lib/ObjectYAML/CodeViewYAMLSymbols.cpp
index 95409fdc3300..6b6a1176628b 100644
--- a/llvm/lib/ObjectYAML/CodeViewYAMLSymbols.cpp
+++ b/llvm/lib/ObjectYAML/CodeViewYAMLSymbols.cpp
@@ -147,7 +147,30 @@ void ScalarEnumerationTraits<CPUType>::enumeration(IO &io, CPUType &Cpu) {
}
void ScalarEnumerationTraits<RegisterId>::enumeration(IO &io, RegisterId &Reg) {
- auto RegNames = getRegisterNames(CPUType::X64);
+ const auto *Header = static_cast<COFF::header *>(io.getContext());
+ assert(Header && "The IO context is not initialized");
+
+ Optional<CPUType> CpuType;
+ ArrayRef<EnumEntry<uint16_t>> RegNames;
+
+ switch (Header->Machine) {
+ case COFF::IMAGE_FILE_MACHINE_I386:
+ CpuType = CPUType::Pentium3;
+ break;
+ case COFF::IMAGE_FILE_MACHINE_AMD64:
+ CpuType = CPUType::X64;
+ break;
+ case COFF::IMAGE_FILE_MACHINE_ARMNT:
+ CpuType = CPUType::ARMNT;
+ break;
+ case COFF::IMAGE_FILE_MACHINE_ARM64:
+ CpuType = CPUType::ARM64;
+ break;
+ }
+
+ if (CpuType)
+ RegNames = getRegisterNames(*CpuType);
+
for (const auto &E : RegNames) {
io.enumCase(Reg, E.Name.str().c_str(), static_cast<RegisterId>(E.Value));
}
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index 3579635f83b5..1053de59dd2d 100644
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -55,7 +55,9 @@
using namespace llvm;
ARMBaseRegisterInfo::ARMBaseRegisterInfo()
- : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC) {}
+ : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC) {
+ ARM_MC::initLLVMToCVRegMapping(this);
+}
static unsigned getFramePointerReg(const ARMSubtarget &STI) {
return STI.useR7AsFramePointer() ? ARM::R7 : ARM::R11;
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
index 765613cf347d..40e8e244e312 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
@@ -87,6 +87,7 @@ void ARMCOFFMCAsmInfoMicrosoft::anchor() { }
ARMCOFFMCAsmInfoMicrosoft::ARMCOFFMCAsmInfoMicrosoft() {
AlignmentIsInBytes = false;
+ SupportsDebugInformation = true;
ExceptionsType = ExceptionHandling::WinEH;
PrivateGlobalPrefix = "$M";
PrivateLabelPrefix = "$M";
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
index 12f3f20cdb43..ced1c692141c 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
@@ -16,6 +16,7 @@
#include "ARMMCAsmInfo.h"
#include "TargetInfo/ARMTargetInfo.h"
#include "llvm/ADT/Triple.h"
+#include "llvm/DebugInfo/CodeView/CodeView.h"
#include "llvm/MC/MCAsmBackend.h"
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCELFStreamer.h"
@@ -205,9 +206,120 @@ static MCInstrInfo *createARMMCInstrInfo() {
return X;
}
+void ARM_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
+ // Mapping from CodeView to MC register id.
+ static const struct {
+ codeview::RegisterId CVReg;
+ MCPhysReg Reg;
+ } RegMap[] = {
+ {codeview::RegisterId::ARM_R0, ARM::R0},
+ {codeview::RegisterId::ARM_R1, ARM::R1},
+ {codeview::RegisterId::ARM_R2, ARM::R2},
+ {codeview::RegisterId::ARM_R3, ARM::R3},
+ {codeview::RegisterId::ARM_R4, ARM::R4},
+ {codeview::RegisterId::ARM_R5, ARM::R5},
+ {codeview::RegisterId::ARM_R6, ARM::R6},
+ {codeview::RegisterId::ARM_R7, ARM::R7},
+ {codeview::RegisterId::ARM_R8, ARM::R8},
+ {codeview::RegisterId::ARM_R9, ARM::R9},
+ {codeview::RegisterId::ARM_R10, ARM::R10},
+ {codeview::RegisterId::ARM_R11, ARM::R11},
+ {codeview::RegisterId::ARM_R12, ARM::R12},
+ {codeview::RegisterId::ARM_SP, ARM::SP},
+ {codeview::RegisterId::ARM_LR, ARM::LR},
+ {codeview::RegisterId::ARM_PC, ARM::PC},
+ {codeview::RegisterId::ARM_CPSR, ARM::CPSR},
+ {codeview::RegisterId::ARM_FPSCR, ARM::FPSCR},
+ {codeview::RegisterId::ARM_FPEXC, ARM::FPEXC},
+ {codeview::RegisterId::ARM_FS0, ARM::S0},
+ {codeview::RegisterId::ARM_FS1, ARM::S1},
+ {codeview::RegisterId::ARM_FS2, ARM::S2},
+ {codeview::RegisterId::ARM_FS3, ARM::S3},
+ {codeview::RegisterId::ARM_FS4, ARM::S4},
+ {codeview::RegisterId::ARM_FS5, ARM::S5},
+ {codeview::RegisterId::ARM_FS6, ARM::S6},
+ {codeview::RegisterId::ARM_FS7, ARM::S7},
+ {codeview::RegisterId::ARM_FS8, ARM::S8},
+ {codeview::RegisterId::ARM_FS9, ARM::S9},
+ {codeview::RegisterId::ARM_FS10, ARM::S10},
+ {codeview::RegisterId::ARM_FS11, ARM::S11},
+ {codeview::RegisterId::ARM_FS12, ARM::S12},
+ {codeview::RegisterId::ARM_FS13, ARM::S13},
+ {codeview::RegisterId::ARM_FS14, ARM::S14},
+ {codeview::RegisterId::ARM_FS15, ARM::S15},
+ {codeview::RegisterId::ARM_FS16, ARM::S16},
+ {codeview::RegisterId::ARM_FS17, ARM::S17},
+ {codeview::RegisterId::ARM_FS18, ARM::S18},
+ {codeview::RegisterId::ARM_FS19, ARM::S19},
+ {codeview::RegisterId::ARM_FS20, ARM::S20},
+ {codeview::RegisterId::ARM_FS21, ARM::S21},
+ {codeview::RegisterId::ARM_FS22, ARM::S22},
+ {codeview::RegisterId::ARM_FS23, ARM::S23},
+ {codeview::RegisterId::ARM_FS24, ARM::S24},
+ {codeview::RegisterId::ARM_FS25, ARM::S25},
+ {codeview::RegisterId::ARM_FS26, ARM::S26},
+ {codeview::RegisterId::ARM_FS27, ARM::S27},
+ {codeview::RegisterId::ARM_FS28, ARM::S28},
+ {codeview::RegisterId::ARM_FS29, ARM::S29},
+ {codeview::RegisterId::ARM_FS30, ARM::S30},
+ {codeview::RegisterId::ARM_FS31, ARM::S31},
+ {codeview::RegisterId::ARM_ND0, ARM::D0},
+ {codeview::RegisterId::ARM_ND1, ARM::D1},
+ {codeview::RegisterId::ARM_ND2, ARM::D2},
+ {codeview::RegisterId::ARM_ND3, ARM::D3},
+ {codeview::RegisterId::ARM_ND4, ARM::D4},
+ {codeview::RegisterId::ARM_ND5, ARM::D5},
+ {codeview::RegisterId::ARM_ND6, ARM::D6},
+ {codeview::RegisterId::ARM_ND7, ARM::D7},
+ {codeview::RegisterId::ARM_ND8, ARM::D8},
+ {codeview::RegisterId::ARM_ND9, ARM::D9},
+ {codeview::RegisterId::ARM_ND10, ARM::D10},
+ {codeview::RegisterId::ARM_ND11, ARM::D11},
+ {codeview::RegisterId::ARM_ND12, ARM::D12},
+ {codeview::RegisterId::ARM_ND13, ARM::D13},
+ {codeview::RegisterId::ARM_ND14, ARM::D14},
+ {codeview::RegisterId::ARM_ND15, ARM::D15},
+ {codeview::RegisterId::ARM_ND16, ARM::D16},
+ {codeview::RegisterId::ARM_ND17, ARM::D17},
+ {codeview::RegisterId::ARM_ND18, ARM::D18},
+ {codeview::RegisterId::ARM_ND19, ARM::D19},
+ {codeview::RegisterId::ARM_ND20, ARM::D20},
+ {codeview::RegisterId::ARM_ND21, ARM::D21},
+ {codeview::RegisterId::ARM_ND22, ARM::D22},
+ {codeview::RegisterId::ARM_ND23, ARM::D23},
+ {codeview::RegisterId::ARM_ND24, ARM::D24},
+ {codeview::RegisterId::ARM_ND25, ARM::D25},
+ {codeview::RegisterId::ARM_ND26, ARM::D26},
+ {codeview::RegisterId::ARM_ND27, ARM::D27},
+ {codeview::RegisterId::ARM_ND28, ARM::D28},
+ {codeview::RegisterId::ARM_ND29, ARM::D29},
+ {codeview::RegisterId::ARM_ND30, ARM::D30},
+ {codeview::RegisterId::ARM_ND31, ARM::D31},
+ {codeview::RegisterId::ARM_NQ0, ARM::Q0},
+ {codeview::RegisterId::ARM_NQ1, ARM::Q1},
+ {codeview::RegisterId::ARM_NQ2, ARM::Q2},
+ {codeview::RegisterId::ARM_NQ3, ARM::Q3},
+ {codeview::RegisterId::ARM_NQ4, ARM::Q4},
+ {codeview::RegisterId::ARM_NQ5, ARM::Q5},
+ {codeview::RegisterId::ARM_NQ6, ARM::Q6},
+ {codeview::RegisterId::ARM_NQ7, ARM::Q7},
+ {codeview::RegisterId::ARM_NQ8, ARM::Q8},
+ {codeview::RegisterId::ARM_NQ9, ARM::Q9},
+ {codeview::RegisterId::ARM_NQ10, ARM::Q10},
+ {codeview::RegisterId::ARM_NQ11, ARM::Q11},
+ {codeview::RegisterId::ARM_NQ12, ARM::Q12},
+ {codeview::RegisterId::ARM_NQ13, ARM::Q13},
+ {codeview::RegisterId::ARM_NQ14, ARM::Q14},
+ {codeview::RegisterId::ARM_NQ15, ARM::Q15},
+ };
+ for (unsigned I = 0; I < array_lengthof(RegMap); ++I)
+ MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg));
+}
+
static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) {
MCRegisterInfo *X = new MCRegisterInfo();
InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
+ ARM_MC::initLLVMToCVRegMapping(X);
return X;
}
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
index 5ab767eaad39..b589c9fab8ce 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
@@ -41,6 +41,7 @@ class raw_pwrite_stream;
namespace ARM_MC {
std::string ParseARMTriple(const Triple &TT, StringRef CPU);
+void initLLVMToCVRegMapping(MCRegisterInfo *MRI);
bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII);
diff --git a/llvm/test/DebugInfo/COFF/ARMNT/arm-register-variables.ll b/llvm/test/DebugInfo/COFF/ARMNT/arm-register-variables.ll
new file mode 100644
index 000000000000..d19cca330b2d
--- /dev/null
+++ b/llvm/test/DebugInfo/COFF/ARMNT/arm-register-variables.ll
@@ -0,0 +1,167 @@
+; RUN: llc < %s -filetype=obj | llvm-readobj --codeview - | FileCheck %s --check-prefix=OBJ
+
+; Generated from:
+
+; volatile int x;
+; int getint(void);
+; void putint(int);
+; static inline int inlineinc(int a) {
+; int b = a + 1;
+; ++x;
+; return b;
+; }
+; void f(int p) {
+; if (p) {
+; int a = getint();
+; int b = inlineinc(a);
+; putint(b);
+; } else {
+; int c = getint();
+; putint(c);
+; }
+; }
+
+; OBJ: Compile3Sym {
+; OBJ-NEXT: Kind: S_COMPILE3 (0x113C)
+; OBJ-NEXT: Language: C (0x0)
+; OBJ-NEXT: Flags [ (0x0)
+; OBJ-NEXT: ]
+; OBJ-NEXT: Machine: ARMNT (0xF4)
+
+; OBJ: LocalSym {
+; OBJ-NEXT: Kind: S_LOCAL (0x113E)
+; OBJ-NEXT: Type: int (0x74)
+; OBJ-NEXT: Flags [ (0x1)
+; OBJ-NEXT: IsParameter (0x1)
+; OBJ-NEXT: ]
+; OBJ-NEXT: VarName: p
+; OBJ-NEXT: }
+; OBJ-NEXT: DefRangeRegisterRelSym {
+; OBJ-NEXT: Kind: S_DEFRANGE_REGISTER_REL (0x1145)
+; OBJ-NEXT: BaseRegister: ARM_SP (0x17)
+; OBJ-NEXT: HasSpilledUDTMember: No
+; OBJ-NEXT: OffsetInParent: 0
+; OBJ-NEXT: BasePointerOffset: 12
+; OBJ-NEXT: LocalVariableAddrRange {
+; OBJ-NEXT: OffsetStart: .text+0x8
+; OBJ-NEXT: ISectStart: 0x0
+; OBJ-NEXT: Range: 0x1A
+; OBJ-NEXT: }
+; OBJ-NEXT: }
+
+; ModuleID = 'test.c'
+source_filename = "test.c"
+target datalayout = "e-m:w-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "thumbv7-pc-windows-msvc19.11.0"
+
+ at x = dso_local global i32 0, align 4, !dbg !0
+
+; Function Attrs: noinline nounwind optnone
+define dso_local arm_aapcs_vfpcc void @f(i32 %p) !dbg !14 {
+entry:
+ %p.addr = alloca i32, align 4
+ %a = alloca i32, align 4
+ %b = alloca i32, align 4
+ %c = alloca i32, align 4
+ store i32 %p, i32* %p.addr, align 4
+ call void @llvm.dbg.declare(metadata i32* %p.addr, metadata !17, metadata !DIExpression()), !dbg !18
+ %0 = load i32, i32* %p.addr, align 4, !dbg !19
+ %tobool = icmp ne i32 %0, 0, !dbg !19
+ br i1 %tobool, label %if.then, label %if.else, !dbg !19
+
+if.then: ; preds = %entry
+ call void @llvm.dbg.declare(metadata i32* %a, metadata !20, metadata !DIExpression()), !dbg !23
+ %call = call arm_aapcs_vfpcc i32 @getint(), !dbg !23
+ store i32 %call, i32* %a, align 4, !dbg !23
+ call void @llvm.dbg.declare(metadata i32* %b, metadata !24, metadata !DIExpression()), !dbg !25
+ %1 = load i32, i32* %a, align 4, !dbg !25
+ %call1 = call arm_aapcs_vfpcc i32 @inlineinc(i32 %1), !dbg !25
+ store i32 %call1, i32* %b, align 4, !dbg !25
+ %2 = load i32, i32* %b, align 4, !dbg !26
+ call arm_aapcs_vfpcc void @putint(i32 %2), !dbg !26
+ br label %if.end, !dbg !27
+
+if.else: ; preds = %entry
+ call void @llvm.dbg.declare(metadata i32* %c, metadata !28, metadata !DIExpression()), !dbg !30
+ %call2 = call arm_aapcs_vfpcc i32 @getint(), !dbg !30
+ store i32 %call2, i32* %c, align 4, !dbg !30
+ %3 = load i32, i32* %c, align 4, !dbg !31
+ call arm_aapcs_vfpcc void @putint(i32 %3), !dbg !31
+ br label %if.end, !dbg !32
+
+if.end: ; preds = %if.else, %if.then
+ ret void, !dbg !33
+}
+
+; Function Attrs: nounwind readnone speculatable willreturn
+declare void @llvm.dbg.declare(metadata, metadata, metadata)
+
+declare dso_local arm_aapcs_vfpcc i32 @getint()
+
+; Function Attrs: noinline nounwind optnone
+define internal arm_aapcs_vfpcc i32 @inlineinc(i32 %a) !dbg !34 {
+entry:
+ %a.addr = alloca i32, align 4
+ %b = alloca i32, align 4
+ store i32 %a, i32* %a.addr, align 4
+ call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !37, metadata !DIExpression()), !dbg !38
+ call void @llvm.dbg.declare(metadata i32* %b, metadata !39, metadata !DIExpression()), !dbg !40
+ %0 = load i32, i32* %a.addr, align 4, !dbg !40
+ %add = add nsw i32 %0, 1, !dbg !40
+ store i32 %add, i32* %b, align 4, !dbg !40
+ %1 = load volatile i32, i32* @x, align 4, !dbg !41
+ %inc = add nsw i32 %1, 1, !dbg !41
+ store volatile i32 %inc, i32* @x, align 4, !dbg !41
+ %2 = load i32, i32* %b, align 4, !dbg !42
+ ret i32 %2, !dbg !42
+}
+
+declare dso_local arm_aapcs_vfpcc void @putint(i32)
+
+!llvm.dbg.cu = !{!2}
+!llvm.module.flags = !{!9, !10, !11, !12}
+!llvm.ident = !{!13}
+
+!0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression())
+!1 = distinct !DIGlobalVariable(name: "x", scope: !2, file: !6, line: 1, type: !7, isLocal: false, isDefinition: true)
+!2 = distinct !DICompileUnit(language: DW_LANG_C99, file: !3, producer: "clang version 12.0.0 (https://github.com/llvm/llvm-project.git fc031d29bea856f2b91a250fd81c5f9fb79dbe07)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !4, globals: !5, nameTableKind: None)
+!3 = !DIFile(filename: "F:\\tmp\\test.c", directory: "F:\\tmp", checksumkind: CSK_MD5, checksum: "5fbd15e58dd6931fc3081de308d52889")
+!4 = !{}
+!5 = !{!0}
+!6 = !DIFile(filename: "test.c", directory: "F:\\tmp", checksumkind: CSK_MD5, checksum: "5fbd15e58dd6931fc3081de308d52889")
+!7 = !DIDerivedType(tag: DW_TAG_volatile_type, baseType: !8)
+!8 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
+!9 = !{i32 2, !"CodeView", i32 1}
+!10 = !{i32 2, !"Debug Info Version", i32 3}
+!11 = !{i32 1, !"wchar_size", i32 2}
+!12 = !{i32 1, !"min_enum_size", i32 4}
+!13 = !{!"clang version 12.0.0 (https://github.com/llvm/llvm-project.git fc031d29bea856f2b91a250fd81c5f9fb79dbe07)"}
+!14 = distinct !DISubprogram(name: "f", scope: !6, file: !6, line: 9, type: !15, scopeLine: 9, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !2, retainedNodes: !4)
+!15 = !DISubroutineType(types: !16)
+!16 = !{null, !8}
+!17 = !DILocalVariable(name: "p", arg: 1, scope: !14, file: !6, line: 9, type: !8)
+!18 = !DILocation(line: 9, scope: !14)
+!19 = !DILocation(line: 10, scope: !14)
+!20 = !DILocalVariable(name: "a", scope: !21, file: !6, line: 11, type: !8)
+!21 = distinct !DILexicalBlock(scope: !22, file: !6, line: 10)
+!22 = distinct !DILexicalBlock(scope: !14, file: !6, line: 10)
+!23 = !DILocation(line: 11, scope: !21)
+!24 = !DILocalVariable(name: "b", scope: !21, file: !6, line: 12, type: !8)
+!25 = !DILocation(line: 12, scope: !21)
+!26 = !DILocation(line: 13, scope: !21)
+!27 = !DILocation(line: 14, scope: !21)
+!28 = !DILocalVariable(name: "c", scope: !29, file: !6, line: 15, type: !8)
+!29 = distinct !DILexicalBlock(scope: !22, file: !6, line: 14)
+!30 = !DILocation(line: 15, scope: !29)
+!31 = !DILocation(line: 16, scope: !29)
+!32 = !DILocation(line: 17, scope: !29)
+!33 = !DILocation(line: 18, scope: !14)
+!34 = distinct !DISubprogram(name: "inlineinc", scope: !6, file: !6, line: 4, type: !35, scopeLine: 4, flags: DIFlagPrototyped, spFlags: DISPFlagLocalToUnit | DISPFlagDefinition, unit: !2, retainedNodes: !4)
+!35 = !DISubroutineType(types: !36)
+!36 = !{!8, !8}
+!37 = !DILocalVariable(name: "a", arg: 1, scope: !34, file: !6, line: 4, type: !8)
+!38 = !DILocation(line: 4, scope: !34)
+!39 = !DILocalVariable(name: "b", scope: !34, file: !6, line: 5, type: !8)
+!40 = !DILocation(line: 5, scope: !34)
+!41 = !DILocation(line: 6, scope: !34)
+!42 = !DILocation(line: 7, scope: !34)
diff --git a/llvm/test/DebugInfo/COFF/ARMNT/lit.local.cfg b/llvm/test/DebugInfo/COFF/ARMNT/lit.local.cfg
new file mode 100644
index 000000000000..98c6700c209d
--- /dev/null
+++ b/llvm/test/DebugInfo/COFF/ARMNT/lit.local.cfg
@@ -0,0 +1,3 @@
+if not 'ARM' in config.root.targets:
+ config.unsupported = True
+
diff --git a/llvm/tools/llvm-pdbutil/MinimalSymbolDumper.cpp b/llvm/tools/llvm-pdbutil/MinimalSymbolDumper.cpp
index 7a06140855f8..787785c34b78 100644
--- a/llvm/tools/llvm-pdbutil/MinimalSymbolDumper.cpp
+++ b/llvm/tools/llvm-pdbutil/MinimalSymbolDumper.cpp
@@ -288,7 +288,18 @@ static std::string formatCookieKind(FrameCookieKind Kind) {
}
static std::string formatRegisterId(RegisterId Id, CPUType Cpu) {
- if (Cpu == CPUType::ARM64) {
+ if (Cpu == CPUType::ARMNT) {
+ switch (Id) {
+#define CV_REGISTERS_ARM
+#define CV_REGISTER(name, val) RETURN_CASE(RegisterId, name, #name)
+#include "llvm/DebugInfo/CodeView/CodeViewRegisters.def"
+#undef CV_REGISTER
+#undef CV_REGISTERS_ARM
+
+ default:
+ break;
+ }
+ } else if (Cpu == CPUType::ARM64) {
switch (Id) {
#define CV_REGISTERS_ARM64
#define CV_REGISTER(name, val) RETURN_CASE(RegisterId, name, #name)
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