[llvm] b5e87c9 - [AArch64][GlobalISel] Add selection support for <8 x s16> G_INSERT_VECTOR_ELT with GPR scalar.

[Yvan Roux via llvm-commits]

Hi Amara,

it seems that this commit broke aarch64_neon_intrinsics.test on AArch64
bots, logs are available here:

http://lab.llvm.org:8011/builders/clang-cmake-aarch64-quick/builds/26577

Cheers,
Yvan

On Fri, 25 Sep 2020 at 18:51, Amara Emerson via llvm-commits <
llvm-commits at lists.llvm.org> wrote:

>
> Author: Amara Emerson
> Date: 2020-09-25T09:51:04-07:00
> New Revision: b5e87c9ef2243ecd65e0ef87a1bf303c0c26db04
>
> URL:
> https://github.com/llvm/llvm-project/commit/b5e87c9ef2243ecd65e0ef87a1bf303c0c26db04
> DIFF:
> https://github.com/llvm/llvm-project/commit/b5e87c9ef2243ecd65e0ef87a1bf303c0c26db04.diff
>
> LOG: [AArch64][GlobalISel] Add selection support for <8 x s16>
> G_INSERT_VECTOR_ELT with GPR scalar.
>
> Fixes the neon intrinsics test in the test suite.
>
> Added:
>
>
> Modified:
>     llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
>     llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir
>
> Removed:
>
>
>
>
> ################################################################################
> diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
> b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
> index 01bd05a2b988..57eb417d2b05 100644
> --- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
> +++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
> @@ -3799,7 +3799,10 @@ static std::pair<unsigned, unsigned>
>  getInsertVecEltOpInfo(const RegisterBank &RB, unsigned EltSize) {
>    unsigned Opc, SubregIdx;
>    if (RB.getID() == AArch64::GPRRegBankID) {
> -    if (EltSize == 32) {
> +    if (EltSize == 16) {
> +      Opc = AArch64::INSvi16gpr;
> +      SubregIdx = AArch64::ssub;
> +    } else if (EltSize == 32) {
>        Opc = AArch64::INSvi32gpr;
>        SubregIdx = AArch64::ssub;
>      } else if (EltSize == 64) {
>
> diff  --git
> a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir
> b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir
> index 5c4a2e1c3544..a311e005a574 100644
> --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir
> +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir
> @@ -1,6 +1,32 @@
>  # NOTE: Assertions have been autogenerated by
> utils/update_mir_test_checks.py
>  # RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown
> -run-pass=instruction-select %s -o - | FileCheck %s
>  ---
> +name:            v8s16_gpr
> +alignment:       4
> +legalized:       true
> +regBankSelected: true
> +tracksRegLiveness: true
> +body:             |
> +  bb.0:
> +    liveins: $q1, $w0
> +
> +    ; CHECK-LABEL: name: v8s16_gpr
> +    ; CHECK: liveins: $q1, $w0
> +    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
> +    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
> +    ; CHECK: [[INSvi16gpr:%[0-9]+]]:fpr128 = INSvi16gpr [[COPY1]], 1,
> [[COPY]]
> +    ; CHECK: $q0 = COPY [[INSvi16gpr]]
> +    ; CHECK: RET_ReallyLR implicit $q0
> +    %0:gpr(s32) = COPY $w0
> +    %trunc:gpr(s16) = G_TRUNC %0
> +    %1:fpr(<8 x s16>) = COPY $q1
> +    %3:gpr(s32) = G_CONSTANT i32 1
> +    %2:fpr(<8 x s16>) = G_INSERT_VECTOR_ELT %1, %trunc:gpr(s16),
> %3:gpr(s32)
> +    $q0 = COPY %2(<8 x s16>)
> +    RET_ReallyLR implicit $q0
> +
> +...
> +---
>  name:            v8s16_fpr
>  alignment:       4
>  legalized:       true
>
>
>
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