<div dir="ltr">Hi Amara,<div><br></div><div>it seems that this commit broke aarch64_neon_intrinsics.test on AArch64 bots, logs are available here:</div><div><br></div><div><a href="http://lab.llvm.org:8011/builders/clang-cmake-aarch64-quick/builds/26577">http://lab.llvm.org:8011/builders/clang-cmake-aarch64-quick/builds/26577</a><br></div><div><br></div><div>Cheers,</div><div>Yvan</div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Fri, 25 Sep 2020 at 18:51, Amara Emerson via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><br>
Author: Amara Emerson<br>
Date: 2020-09-25T09:51:04-07:00<br>
New Revision: b5e87c9ef2243ecd65e0ef87a1bf303c0c26db04<br>
<br>
URL: <a href="https://github.com/llvm/llvm-project/commit/b5e87c9ef2243ecd65e0ef87a1bf303c0c26db04" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/b5e87c9ef2243ecd65e0ef87a1bf303c0c26db04</a><br>
DIFF: <a href="https://github.com/llvm/llvm-project/commit/b5e87c9ef2243ecd65e0ef87a1bf303c0c26db04.diff" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/b5e87c9ef2243ecd65e0ef87a1bf303c0c26db04.diff</a><br>
<br>
LOG: [AArch64][GlobalISel] Add selection support for <8 x s16>  G_INSERT_VECTOR_ELT with GPR scalar.<br>
<br>
Fixes the neon intrinsics test in the test suite.<br>
<br>
Added: <br>
<br>
<br>
Modified: <br>
    llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp<br>
    llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir<br>
<br>
Removed: <br>
<br>
<br>
<br>
################################################################################<br>
diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp<br>
index 01bd05a2b988..57eb417d2b05 100644<br>
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp<br>
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp<br>
@@ -3799,7 +3799,10 @@ static std::pair<unsigned, unsigned><br>
 getInsertVecEltOpInfo(const RegisterBank &RB, unsigned EltSize) {<br>
   unsigned Opc, SubregIdx;<br>
   if (RB.getID() == AArch64::GPRRegBankID) {<br>
-    if (EltSize == 32) {<br>
+    if (EltSize == 16) {<br>
+      Opc = AArch64::INSvi16gpr;<br>
+      SubregIdx = AArch64::ssub;<br>
+    } else if (EltSize == 32) {<br>
       Opc = AArch64::INSvi32gpr;<br>
       SubregIdx = AArch64::ssub;<br>
     } else if (EltSize == 64) {<br>
<br>
diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir<br>
index 5c4a2e1c3544..a311e005a574 100644<br>
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir<br>
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir<br>
@@ -1,6 +1,32 @@<br>
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py<br>
 # RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=instruction-select %s -o - | FileCheck %s<br>
 ---<br>
+name:            v8s16_gpr<br>
+alignment:       4<br>
+legalized:       true<br>
+regBankSelected: true<br>
+tracksRegLiveness: true<br>
+body:             |<br>
+  bb.0:<br>
+    liveins: $q1, $w0<br>
+<br>
+    ; CHECK-LABEL: name: v8s16_gpr<br>
+    ; CHECK: liveins: $q1, $w0<br>
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0<br>
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1<br>
+    ; CHECK: [[INSvi16gpr:%[0-9]+]]:fpr128 = INSvi16gpr [[COPY1]], 1, [[COPY]]<br>
+    ; CHECK: $q0 = COPY [[INSvi16gpr]]<br>
+    ; CHECK: RET_ReallyLR implicit $q0<br>
+    %0:gpr(s32) = COPY $w0<br>
+    %trunc:gpr(s16) = G_TRUNC %0<br>
+    %1:fpr(<8 x s16>) = COPY $q1<br>
+    %3:gpr(s32) = G_CONSTANT i32 1<br>
+    %2:fpr(<8 x s16>) = G_INSERT_VECTOR_ELT %1, %trunc:gpr(s16), %3:gpr(s32)<br>
+    $q0 = COPY %2(<8 x s16>)<br>
+    RET_ReallyLR implicit $q0<br>
+<br>
+...<br>
+---<br>
 name:            v8s16_fpr<br>
 alignment:       4<br>
 legalized:       true<br>
<br>
<br>
<br>
_______________________________________________<br>
llvm-commits mailing list<br>
<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a><br>
<a href="https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a><br>
</blockquote></div>