[PATCH] D87796: [SVE][WIP] Lower fixed length VECREDUCE_ADD to Scalable

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

I think the NEON code is trying to avoid producing an extra instruction if the result ends up getting used by a vector operation.  SelectionDAG technically allows instructions that produce an i64 result to return it in a floating-point register, but it doesn't work very well in practice: the operations that consume it will force it back into a GPR.  This is one of the issues GlobalISel's RegBankSelect solves.

It should be possible to make the patterns for SVE do the same thing, I think?


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https://reviews.llvm.org/D87796