[PATCH] D87796: [SVE][WIP] Lower fixed length VECREDUCE_ADD to Scalable

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally created this revision.
cameron.mcinally added reviewers: dancgr, paulwalker-arm, sdesmalen, eli.friedman.
Herald added subscribers: llvm-commits, psnobl, hiraditya, tschuett.
Herald added a reviewer: rengolin.
Herald added a reviewer: efriedma.
Herald added a project: LLVM.
cameron.mcinally requested review of this revision.

This isn't really ready for review, but more like an RFC...

There are a number of VECREDUCE_* nodes that can be lowered to SVE instructions. The integer instructions are:

  UADDV, SADDV, SMAXV, SMINV, UMAXV, and UMINV

UADDV/SADDV are a little different from the rest in that they always return an i64 result, where the other results are of the vector element type.

That is fine, but the TableGen pattern aren't straight-forward. The patterns for UADDV/SADDV return a scalar i64. The other patterns return a NEON vector register, from which the scalar result is later extracted. I'd like to understand why that 'insert-then-extract' decision was made. Here is the code in question:

  class SVE_2_Op_Pat_Reduce_To_Neon<ValueType vtd, SDPatternOperator op, ValueType vt1,
                     ValueType vt2, Instruction inst, SubRegIndex sub>
  : Pat<(vtd (op vt1:$Op1, vt2:$Op2)),
        (INSERT_SUBREG (vtd (IMPLICIT_DEF)), (inst $Op1, $Op2), sub)>;

And then the lowering code extracts it back out:

  static SDValue getReductionSDNode(unsigned Op, SDLoc DL, SDValue ScalarOp,
                                    SelectionDAG &DAG) {
    SDValue VecOp = ScalarOp.getOperand(0);
    auto Rdx = DAG.getNode(Op, DL, VecOp.getSimpleValueType(), VecOp);
    return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ScalarOp.getValueType(), Rdx,
                       DAG.getConstant(0, DL, MVT::i64));
  }

What was the motivation for that design?

In the current state, we'll probably need an unfortunate amount of code duplication, or special cases in the lowering code, for SADDV/UADDV. I'd like to avoid that if possible...


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D87796

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D87796.292324.patch
Type: text/x-patch
Size: 11343 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200916/27f67e7c/attachment.bin>