[PATCH] D87351: AMDGPU/GlobalISel/Emitter Recognize additional 'same operand checks'

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

Can you add tests for the min3/max3/med3 patterns? I think this is what was blocking those



================
Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir:27-28
     ; CHECK: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[S_LOAD_DWORDX2_IMM]]
     ; CHECK: %12:vreg_64 = nofpexcept V_ADD_F64 0, [[COPY3]], 1, [[COPY4]], 0, 0, implicit $mode, implicit $exec
-    ; CHECK: %13:vreg_64 = nofpexcept V_FLOOR_F64_e64 0, %12, 0, 0, implicit $mode, implicit $exec
-    ; CHECK: %15:vreg_64 = nofpexcept V_ADD_F64 0, %12, 1, %13, 0, 0, implicit $mode, implicit $exec
+    ; CHECK: %15:vreg_64 = nofpexcept V_FRACT_F64_e64 0, %12, 0, 0, implicit $mode, implicit $exec
     ; CHECK: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[COPY1]]
----------------
Is this pattern really correct? It should probably be moved into a combine instead of a selection pattern if so


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D87351/new/

https://reviews.llvm.org/D87351