[PATCH] D86022: [ARM] Allow tail predication of VLDn

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: samparker, samtebbs, SjoerdMeijer, efriedma, ostannard, simon_tatham.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls.
Herald added a project: LLVM.
dmgreen requested review of this revision.

VLD2 instructions cannot be predicated, so we cannot tail predicate them from autovec. From intrinsics though, they should be valid as they will just end up loading extra values into off vector lanes, not effecting the on lanes. The same is true for loads in general where so long as we are not using the other vector lanes, an unpredicated load can be converted to a predicated one.

This marks VLD2 and VLD4 instructions as validForTailPredication and allows any unpredicated load in tail predication loop, which I believe will be valid given the other checks we have (but may be mistaken. Some checks I could think of appear to be missing (to do with moving between vector lanes), but that seems to be an orthogonal issue).


https://reviews.llvm.org/D86022

Files:
  llvm/lib/Target/ARM/ARMInstrMVE.td
  llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredload.ll

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