[PATCH] D85772: [AMDGPU] Fix FP/BP spills when MUBUF constant offset exceeded

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll:570
 }
 
+; GCN-LABEL: {{^}}spill_fp_to_memory_scratch_reg_needed_mubuf_offset
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Can you add a comment explaining the point of the test?


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Comment at: llvm/test/CodeGen/AMDGPU/stack-realign.ll:258
+define void @no_free_regs_spill_bp_to_memory(<32 x i32> %a, i32 %b) #0 {
+; If there are no free SGPRs or VGPRs avaialbe we must spill the BP to memory.
+
----------------
Typo avaialbe


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Comment at: llvm/test/CodeGen/AMDGPU/stack-realign.ll:282
+
+  call void asm sideeffect "; clobber all VGPRs except CSR v40",
+    "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9}
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You can shrink the register list with amdgpu-waves-per-eu to restrict the number of registers


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D85772/new/

https://reviews.llvm.org/D85772