[PATCH] D84449: AMDGPU/GlobalISel: Manually select llvm.amdgcn.writelane

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D84449#2210301 <https://reviews.llvm.org/D84449#2210301>, @arsenm wrote:

> In D84449#2210208 <https://reviews.llvm.org/D84449#2210208>, @foad wrote:
>
>> Pre-gfx10 `writelane v0, m0, s0` is legal, isn't it? Does your implementation allow for that? You don't seem to have any tests for that case.
>
> This is covered by @test_writelane_m0_s_v, but it looks like it ends up swapping the registers:
>
>   ; GFX7-NEXT:    s_mov_b32 s0, m0
>   ; GFX7-NEXT:    s_mov_b32 m0, s2
>   ; GFX7-NEXT:    v_writelane_b32 v0, s0, m0

I'm not sure there's a principled way to fold this during selection. I think handling this correctly would require us to finally stop treating m0 as a reserved register


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