[llvm] 04cf4a5 - [AMDGPU] Lower frem f16
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 5 01:10:25 PDT 2020
Author: Jay Foad
Date: 2020-08-05T09:08:40+01:00
New Revision: 04cf4a5a65576f286ca2e8a1aae7584def512761
URL: https://github.com/llvm/llvm-project/commit/04cf4a5a65576f286ca2e8a1aae7584def512761
DIFF: https://github.com/llvm/llvm-project/commit/04cf4a5a65576f286ca2e8a1aae7584def512761.diff
LOG: [AMDGPU] Lower frem f16
Without this it would fail to select on subtargets that have 16-bit
instructions.
Differential Revision: https://reviews.llvm.org/D84517
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
llvm/test/CodeGen/AMDGPU/frem.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index a697df5553b7..14e05507218e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -320,6 +320,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
+ setOperationAction(ISD::FREM, MVT::f16, Custom);
setOperationAction(ISD::FREM, MVT::f32, Custom);
setOperationAction(ISD::FREM, MVT::f64, Custom);
diff --git a/llvm/test/CodeGen/AMDGPU/frem.ll b/llvm/test/CodeGen/AMDGPU/frem.ll
index 0414384dabe4..09c9716024c2 100644
--- a/llvm/test/CodeGen/AMDGPU/frem.ll
+++ b/llvm/test/CodeGen/AMDGPU/frem.ll
@@ -3,6 +3,215 @@
; RUN: llc -amdgpu-scalarize-global-loads=false -enable-misched=0 -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,CI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -enable-misched=0 -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
+define amdgpu_kernel void @frem_f16(half addrspace(1)* %out, half addrspace(1)* %in1,
+; SI-LABEL: frem_f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_mov_b32 s0, s4
+; SI-NEXT: s_mov_b32 s1, s5
+; SI-NEXT: s_mov_b32 s4, s6
+; SI-NEXT: s_mov_b32 s5, s7
+; SI-NEXT: s_mov_b32 s6, s2
+; SI-NEXT: s_mov_b32 s7, s3
+; SI-NEXT: s_mov_b32 s10, s2
+; SI-NEXT: s_mov_b32 s11, s3
+; SI-NEXT: buffer_load_ushort v0, off, s[4:7], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 offset:8
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_div_scale_f32 v2, vcc, v0, v1, v0
+; SI-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; SI-NEXT: v_rcp_f32_e32 v4, v3
+; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; SI-NEXT: v_fma_f32 v5, -v3, v4, 1.0
+; SI-NEXT: v_fma_f32 v4, v5, v4, v4
+; SI-NEXT: v_mul_f32_e32 v5, v2, v4
+; SI-NEXT: v_fma_f32 v6, -v3, v5, v2
+; SI-NEXT: v_fma_f32 v5, v6, v4, v5
+; SI-NEXT: v_fma_f32 v2, -v3, v5, v2
+; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; SI-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; SI-NEXT: v_div_fixup_f32 v2, v2, v1, v0
+; SI-NEXT: v_trunc_f32_e32 v2, v2
+; SI-NEXT: v_fma_f32 v0, -v2, v1, v0
+; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; CI-LABEL: frem_f16:
+; CI: ; %bb.0:
+; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
+; CI-NEXT: s_mov_b32 s11, 0xf000
+; CI-NEXT: s_mov_b32 s10, -1
+; CI-NEXT: s_mov_b32 s2, s10
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: s_mov_b32 s8, s4
+; CI-NEXT: s_mov_b32 s9, s5
+; CI-NEXT: s_mov_b32 s4, s6
+; CI-NEXT: s_mov_b32 s5, s7
+; CI-NEXT: s_mov_b32 s3, s11
+; CI-NEXT: s_mov_b32 s6, s10
+; CI-NEXT: s_mov_b32 s7, s11
+; CI-NEXT: buffer_load_ushort v0, off, s[4:7], 0
+; CI-NEXT: buffer_load_ushort v1, off, s[0:3], 0 offset:8
+; CI-NEXT: s_waitcnt vmcnt(1)
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: s_waitcnt vmcnt(0)
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; CI-NEXT: v_div_scale_f32 v3, s[0:1], v1, v1, v0
+; CI-NEXT: v_div_scale_f32 v2, vcc, v0, v1, v0
+; CI-NEXT: v_rcp_f32_e32 v4, v3
+; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; CI-NEXT: v_fma_f32 v5, -v3, v4, 1.0
+; CI-NEXT: v_fma_f32 v4, v5, v4, v4
+; CI-NEXT: v_mul_f32_e32 v5, v2, v4
+; CI-NEXT: v_fma_f32 v6, -v3, v5, v2
+; CI-NEXT: v_fma_f32 v5, v6, v4, v5
+; CI-NEXT: v_fma_f32 v2, -v3, v5, v2
+; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; CI-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; CI-NEXT: v_div_fixup_f32 v2, v2, v1, v0
+; CI-NEXT: v_trunc_f32_e32 v2, v2
+; CI-NEXT: v_fma_f32 v0, -v2, v1, v0
+; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; CI-NEXT: buffer_store_short v0, off, s[8:11], 0
+; CI-NEXT: s_endpgm
+;
+; VI-LABEL: frem_f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v2, s6
+; VI-NEXT: s_add_u32 s0, s0, 8
+; VI-NEXT: v_mov_b32_e32 v3, s7
+; VI-NEXT: s_addc_u32 s1, s1, 0
+; VI-NEXT: flat_load_ushort v4, v[2:3]
+; VI-NEXT: v_mov_b32_e32 v3, s1
+; VI-NEXT: v_mov_b32_e32 v2, s0
+; VI-NEXT: flat_load_ushort v2, v[2:3]
+; VI-NEXT: v_mov_b32_e32 v0, s4
+; VI-NEXT: v_mov_b32_e32 v1, s5
+; VI-NEXT: s_waitcnt vmcnt(1) lgkmcnt(1)
+; VI-NEXT: v_cvt_f32_f16_e32 v3, v4
+; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; VI-NEXT: v_cvt_f32_f16_e32 v5, v2
+; VI-NEXT: v_rcp_f32_e32 v5, v5
+; VI-NEXT: v_mul_f32_e32 v3, v3, v5
+; VI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; VI-NEXT: v_div_fixup_f16 v3, v3, v2, v4
+; VI-NEXT: v_trunc_f16_e32 v3, v3
+; VI-NEXT: v_fma_f16 v2, -v3, v2, v4
+; VI-NEXT: flat_store_short v[0:1], v2
+; VI-NEXT: s_endpgm
+ half addrspace(1)* %in2) #0 {
+ %gep2 = getelementptr half, half addrspace(1)* %in2, i32 4
+ %r0 = load half, half addrspace(1)* %in1, align 4
+ %r1 = load half, half addrspace(1)* %gep2, align 4
+ %r2 = frem half %r0, %r1
+ store half %r2, half addrspace(1)* %out, align 4
+ ret void
+}
+
+define amdgpu_kernel void @unsafe_frem_f16(half addrspace(1)* %out, half addrspace(1)* %in1,
+; SI-LABEL: unsafe_frem_f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_mov_b32 s0, s4
+; SI-NEXT: s_mov_b32 s1, s5
+; SI-NEXT: s_mov_b32 s4, s6
+; SI-NEXT: s_mov_b32 s5, s7
+; SI-NEXT: s_mov_b32 s6, s2
+; SI-NEXT: s_mov_b32 s7, s3
+; SI-NEXT: s_mov_b32 s10, s2
+; SI-NEXT: s_mov_b32 s11, s3
+; SI-NEXT: buffer_load_ushort v0, off, s[4:7], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 offset:8
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_rcp_f32_e32 v2, v1
+; SI-NEXT: v_mul_f32_e32 v2, v0, v2
+; SI-NEXT: v_trunc_f32_e32 v2, v2
+; SI-NEXT: v_fma_f32 v0, -v2, v1, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; CI-LABEL: unsafe_frem_f16:
+; CI: ; %bb.0:
+; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
+; CI-NEXT: s_mov_b32 s11, 0xf000
+; CI-NEXT: s_mov_b32 s10, -1
+; CI-NEXT: s_mov_b32 s2, s10
+; CI-NEXT: s_mov_b32 s3, s11
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: buffer_load_ushort v1, off, s[0:3], 0 offset:8
+; CI-NEXT: s_mov_b32 s8, s4
+; CI-NEXT: s_mov_b32 s9, s5
+; CI-NEXT: s_mov_b32 s4, s6
+; CI-NEXT: s_mov_b32 s5, s7
+; CI-NEXT: s_mov_b32 s6, s10
+; CI-NEXT: s_mov_b32 s7, s11
+; CI-NEXT: buffer_load_ushort v0, off, s[4:7], 0
+; CI-NEXT: s_waitcnt vmcnt(1)
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; CI-NEXT: v_rcp_f32_e32 v2, v1
+; CI-NEXT: s_waitcnt vmcnt(0)
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_mul_f32_e32 v2, v0, v2
+; CI-NEXT: v_trunc_f32_e32 v2, v2
+; CI-NEXT: v_fma_f32 v0, -v2, v1, v0
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; CI-NEXT: buffer_store_short v0, off, s[8:11], 0
+; CI-NEXT: s_endpgm
+;
+; VI-LABEL: unsafe_frem_f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v2, s6
+; VI-NEXT: s_add_u32 s0, s0, 8
+; VI-NEXT: v_mov_b32_e32 v3, s7
+; VI-NEXT: s_addc_u32 s1, s1, 0
+; VI-NEXT: flat_load_ushort v4, v[2:3]
+; VI-NEXT: v_mov_b32_e32 v3, s1
+; VI-NEXT: v_mov_b32_e32 v2, s0
+; VI-NEXT: flat_load_ushort v2, v[2:3]
+; VI-NEXT: v_mov_b32_e32 v0, s4
+; VI-NEXT: v_mov_b32_e32 v1, s5
+; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; VI-NEXT: v_rcp_f16_e32 v3, v2
+; VI-NEXT: v_mul_f16_e32 v3, v4, v3
+; VI-NEXT: v_trunc_f16_e32 v3, v3
+; VI-NEXT: v_fma_f16 v2, -v3, v2, v4
+; VI-NEXT: flat_store_short v[0:1], v2
+; VI-NEXT: s_endpgm
+ half addrspace(1)* %in2) #1 {
+ %gep2 = getelementptr half, half addrspace(1)* %in2, i32 4
+ %r0 = load half, half addrspace(1)* %in1, align 4
+ %r1 = load half, half addrspace(1)* %gep2, align 4
+ %r2 = frem half %r0, %r1
+ store half %r2, half addrspace(1)* %out, align 4
+ ret void
+}
+
define amdgpu_kernel void @frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
; SI-LABEL: frem_f32:
; SI: ; %bb.0:
@@ -422,6 +631,464 @@ define amdgpu_kernel void @unsafe_frem_f64(double addrspace(1)* %out, double add
ret void
}
+define amdgpu_kernel void @frem_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in1,
+; SI-LABEL: frem_v2f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_mov_b32 s0, s4
+; SI-NEXT: s_mov_b32 s1, s5
+; SI-NEXT: s_mov_b32 s4, s6
+; SI-NEXT: s_mov_b32 s5, s7
+; SI-NEXT: s_mov_b32 s6, s2
+; SI-NEXT: s_mov_b32 s7, s3
+; SI-NEXT: s_mov_b32 s10, s2
+; SI-NEXT: s_mov_b32 s11, s3
+; SI-NEXT: buffer_load_dword v0, off, s[4:7], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: buffer_load_dword v2, off, s[8:11], 0 offset:16
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v2
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_div_scale_f32 v4, vcc, v0, v2, v0
+; SI-NEXT: v_div_scale_f32 v5, s[4:5], v2, v2, v0
+; SI-NEXT: v_rcp_f32_e32 v6, v5
+; SI-NEXT: s_mov_b32 s6, 3
+; SI-NEXT: s_mov_b32 s7, 0
+; SI-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
+; SI-NEXT: v_fma_f32 v7, -v5, v6, 1.0
+; SI-NEXT: v_fma_f32 v6, v7, v6, v6
+; SI-NEXT: v_mul_f32_e32 v7, v4, v6
+; SI-NEXT: v_fma_f32 v8, -v5, v7, v4
+; SI-NEXT: v_fma_f32 v7, v8, v6, v7
+; SI-NEXT: v_fma_f32 v4, -v5, v7, v4
+; SI-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
+; SI-NEXT: v_div_fmas_f32 v4, v4, v6, v7
+; SI-NEXT: v_div_fixup_f32 v4, v4, v2, v0
+; SI-NEXT: v_trunc_f32_e32 v4, v4
+; SI-NEXT: v_fma_f32 v0, -v4, v2, v0
+; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_div_scale_f32 v2, vcc, v1, v3, v1
+; SI-NEXT: v_div_scale_f32 v4, s[4:5], v3, v3, v1
+; SI-NEXT: v_rcp_f32_e32 v5, v4
+; SI-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
+; SI-NEXT: v_fma_f32 v6, -v4, v5, 1.0
+; SI-NEXT: v_fma_f32 v5, v6, v5, v5
+; SI-NEXT: v_mul_f32_e32 v6, v2, v5
+; SI-NEXT: v_fma_f32 v7, -v4, v6, v2
+; SI-NEXT: v_fma_f32 v6, v7, v5, v6
+; SI-NEXT: v_fma_f32 v2, -v4, v6, v2
+; SI-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
+; SI-NEXT: v_div_fmas_f32 v2, v2, v5, v6
+; SI-NEXT: v_div_fixup_f32 v2, v2, v3, v1
+; SI-NEXT: v_trunc_f32_e32 v2, v2
+; SI-NEXT: v_fma_f32 v1, -v2, v3, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; CI-LABEL: frem_v2f16:
+; CI: ; %bb.0:
+; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; CI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
+; CI-NEXT: s_mov_b32 s3, 0xf000
+; CI-NEXT: s_mov_b32 s2, -1
+; CI-NEXT: s_mov_b32 s10, s2
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: s_mov_b32 s0, s4
+; CI-NEXT: s_mov_b32 s1, s5
+; CI-NEXT: s_mov_b32 s4, s6
+; CI-NEXT: s_mov_b32 s5, s7
+; CI-NEXT: s_mov_b32 s11, s3
+; CI-NEXT: s_mov_b32 s6, s2
+; CI-NEXT: s_mov_b32 s7, s3
+; CI-NEXT: buffer_load_dword v0, off, s[4:7], 0
+; CI-NEXT: buffer_load_dword v2, off, s[8:11], 0 offset:16
+; CI-NEXT: s_mov_b32 s6, 3
+; CI-NEXT: s_mov_b32 s7, 0
+; CI-NEXT: s_waitcnt vmcnt(1)
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v0
+; CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; CI-NEXT: s_waitcnt vmcnt(0)
+; CI-NEXT: v_cvt_f32_f16_e32 v3, v2
+; CI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; CI-NEXT: v_div_scale_f32 v5, s[4:5], v2, v2, v0
+; CI-NEXT: v_div_scale_f32 v4, vcc, v0, v2, v0
+; CI-NEXT: v_rcp_f32_e32 v6, v5
+; CI-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
+; CI-NEXT: v_fma_f32 v7, -v5, v6, 1.0
+; CI-NEXT: v_fma_f32 v6, v7, v6, v6
+; CI-NEXT: v_mul_f32_e32 v7, v4, v6
+; CI-NEXT: v_fma_f32 v8, -v5, v7, v4
+; CI-NEXT: v_fma_f32 v7, v8, v6, v7
+; CI-NEXT: v_fma_f32 v4, -v5, v7, v4
+; CI-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
+; CI-NEXT: v_div_fmas_f32 v4, v4, v6, v7
+; CI-NEXT: v_div_fixup_f32 v4, v4, v2, v0
+; CI-NEXT: v_trunc_f32_e32 v4, v4
+; CI-NEXT: v_fma_f32 v0, -v4, v2, v0
+; CI-NEXT: v_div_scale_f32 v4, s[4:5], v3, v3, v1
+; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; CI-NEXT: v_div_scale_f32 v2, vcc, v1, v3, v1
+; CI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; CI-NEXT: v_rcp_f32_e32 v5, v4
+; CI-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
+; CI-NEXT: v_fma_f32 v6, -v4, v5, 1.0
+; CI-NEXT: v_fma_f32 v5, v6, v5, v5
+; CI-NEXT: v_mul_f32_e32 v6, v2, v5
+; CI-NEXT: v_fma_f32 v7, -v4, v6, v2
+; CI-NEXT: v_fma_f32 v6, v7, v5, v6
+; CI-NEXT: v_fma_f32 v2, -v4, v6, v2
+; CI-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
+; CI-NEXT: v_div_fmas_f32 v2, v2, v5, v6
+; CI-NEXT: v_div_fixup_f32 v2, v2, v3, v1
+; CI-NEXT: v_trunc_f32_e32 v2, v2
+; CI-NEXT: v_fma_f32 v1, -v2, v3, v1
+; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; CI-NEXT: v_or_b32_e32 v0, v1, v0
+; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; CI-NEXT: s_endpgm
+;
+; VI-LABEL: frem_v2f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v2, s6
+; VI-NEXT: s_add_u32 s0, s0, 16
+; VI-NEXT: v_mov_b32_e32 v3, s7
+; VI-NEXT: s_addc_u32 s1, s1, 0
+; VI-NEXT: flat_load_dword v4, v[2:3]
+; VI-NEXT: v_mov_b32_e32 v3, s1
+; VI-NEXT: v_mov_b32_e32 v2, s0
+; VI-NEXT: flat_load_dword v2, v[2:3]
+; VI-NEXT: v_mov_b32_e32 v0, s4
+; VI-NEXT: v_mov_b32_e32 v1, s5
+; VI-NEXT: s_waitcnt vmcnt(1) lgkmcnt(1)
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v4
+; VI-NEXT: v_cvt_f32_f16_e32 v5, v3
+; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v2
+; VI-NEXT: v_cvt_f32_f16_e32 v7, v6
+; VI-NEXT: v_rcp_f32_e32 v7, v7
+; VI-NEXT: v_mul_f32_e32 v5, v5, v7
+; VI-NEXT: v_cvt_f16_f32_e32 v5, v5
+; VI-NEXT: v_div_fixup_f16 v5, v5, v6, v3
+; VI-NEXT: v_trunc_f16_e32 v5, v5
+; VI-NEXT: v_fma_f16 v3, -v5, v6, v3
+; VI-NEXT: v_cvt_f32_f16_e32 v6, v2
+; VI-NEXT: v_cvt_f32_f16_e32 v5, v4
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_rcp_f32_e32 v6, v6
+; VI-NEXT: v_mul_f32_e32 v5, v5, v6
+; VI-NEXT: v_cvt_f16_f32_e32 v5, v5
+; VI-NEXT: v_div_fixup_f16 v5, v5, v2, v4
+; VI-NEXT: v_trunc_f16_e32 v5, v5
+; VI-NEXT: v_fma_f16 v2, -v5, v2, v4
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_endpgm
+ <2 x half> addrspace(1)* %in2) #0 {
+ %gep2 = getelementptr <2 x half>, <2 x half> addrspace(1)* %in2, i32 4
+ %r0 = load <2 x half>, <2 x half> addrspace(1)* %in1, align 8
+ %r1 = load <2 x half>, <2 x half> addrspace(1)* %gep2, align 8
+ %r2 = frem <2 x half> %r0, %r1
+ store <2 x half> %r2, <2 x half> addrspace(1)* %out, align 8
+ ret void
+}
+
+define amdgpu_kernel void @frem_v4f16(<4 x half> addrspace(1)* %out, <4 x half> addrspace(1)* %in1,
+; SI-LABEL: frem_v4f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_mov_b32 s0, s4
+; SI-NEXT: s_mov_b32 s1, s5
+; SI-NEXT: s_mov_b32 s4, s6
+; SI-NEXT: s_mov_b32 s5, s7
+; SI-NEXT: s_mov_b32 s6, s2
+; SI-NEXT: s_mov_b32 s7, s3
+; SI-NEXT: s_mov_b32 s10, s2
+; SI-NEXT: s_mov_b32 s11, s3
+; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v1
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v0
+; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0 offset:32
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v6, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v7, v1
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_div_scale_f32 v8, vcc, v5, v1, v5
+; SI-NEXT: v_div_scale_f32 v9, s[4:5], v1, v1, v5
+; SI-NEXT: v_rcp_f32_e32 v10, v9
+; SI-NEXT: s_mov_b32 s6, 3
+; SI-NEXT: s_mov_b32 s7, 0
+; SI-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
+; SI-NEXT: v_fma_f32 v11, -v9, v10, 1.0
+; SI-NEXT: v_fma_f32 v10, v11, v10, v10
+; SI-NEXT: v_mul_f32_e32 v11, v8, v10
+; SI-NEXT: v_fma_f32 v12, -v9, v11, v8
+; SI-NEXT: v_fma_f32 v11, v12, v10, v11
+; SI-NEXT: v_fma_f32 v8, -v9, v11, v8
+; SI-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
+; SI-NEXT: v_div_fmas_f32 v8, v8, v10, v11
+; SI-NEXT: v_div_fixup_f32 v8, v8, v1, v5
+; SI-NEXT: v_trunc_f32_e32 v8, v8
+; SI-NEXT: v_fma_f32 v1, -v8, v1, v5
+; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_div_scale_f32 v5, vcc, v4, v7, v4
+; SI-NEXT: v_div_scale_f32 v8, s[4:5], v7, v7, v4
+; SI-NEXT: v_rcp_f32_e32 v9, v8
+; SI-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
+; SI-NEXT: v_fma_f32 v10, -v8, v9, 1.0
+; SI-NEXT: v_fma_f32 v9, v10, v9, v9
+; SI-NEXT: v_mul_f32_e32 v10, v5, v9
+; SI-NEXT: v_fma_f32 v11, -v8, v10, v5
+; SI-NEXT: v_fma_f32 v10, v11, v9, v10
+; SI-NEXT: v_fma_f32 v5, -v8, v10, v5
+; SI-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
+; SI-NEXT: v_div_fmas_f32 v5, v5, v9, v10
+; SI-NEXT: v_div_fixup_f32 v5, v5, v7, v4
+; SI-NEXT: v_trunc_f32_e32 v5, v5
+; SI-NEXT: v_fma_f32 v4, -v5, v7, v4
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
+; SI-NEXT: v_or_b32_e32 v1, v4, v1
+; SI-NEXT: v_div_scale_f32 v4, vcc, v3, v0, v3
+; SI-NEXT: v_div_scale_f32 v5, s[4:5], v0, v0, v3
+; SI-NEXT: v_rcp_f32_e32 v7, v5
+; SI-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
+; SI-NEXT: v_fma_f32 v8, -v5, v7, 1.0
+; SI-NEXT: v_fma_f32 v7, v8, v7, v7
+; SI-NEXT: v_mul_f32_e32 v8, v4, v7
+; SI-NEXT: v_fma_f32 v9, -v5, v8, v4
+; SI-NEXT: v_fma_f32 v8, v9, v7, v8
+; SI-NEXT: v_fma_f32 v4, -v5, v8, v4
+; SI-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
+; SI-NEXT: v_div_fmas_f32 v4, v4, v7, v8
+; SI-NEXT: v_div_fixup_f32 v4, v4, v0, v3
+; SI-NEXT: v_trunc_f32_e32 v4, v4
+; SI-NEXT: v_fma_f32 v0, -v4, v0, v3
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_div_scale_f32 v3, vcc, v2, v6, v2
+; SI-NEXT: v_div_scale_f32 v4, s[4:5], v6, v6, v2
+; SI-NEXT: v_rcp_f32_e32 v5, v4
+; SI-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
+; SI-NEXT: v_fma_f32 v7, -v4, v5, 1.0
+; SI-NEXT: v_fma_f32 v5, v7, v5, v5
+; SI-NEXT: v_mul_f32_e32 v7, v3, v5
+; SI-NEXT: v_fma_f32 v8, -v4, v7, v3
+; SI-NEXT: v_fma_f32 v7, v8, v5, v7
+; SI-NEXT: v_fma_f32 v3, -v4, v7, v3
+; SI-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
+; SI-NEXT: v_div_fmas_f32 v3, v3, v5, v7
+; SI-NEXT: v_div_fixup_f32 v3, v3, v6, v2
+; SI-NEXT: v_trunc_f32_e32 v3, v3
+; SI-NEXT: v_fma_f32 v2, -v3, v6, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_or_b32_e32 v0, v2, v0
+; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; CI-LABEL: frem_v4f16:
+; CI: ; %bb.0:
+; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; CI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
+; CI-NEXT: s_mov_b32 s3, 0xf000
+; CI-NEXT: s_mov_b32 s2, -1
+; CI-NEXT: s_mov_b32 s10, s2
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: s_mov_b32 s0, s4
+; CI-NEXT: s_mov_b32 s1, s5
+; CI-NEXT: s_mov_b32 s4, s6
+; CI-NEXT: s_mov_b32 s5, s7
+; CI-NEXT: s_mov_b32 s6, s2
+; CI-NEXT: s_mov_b32 s7, s3
+; CI-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0
+; CI-NEXT: s_mov_b32 s11, s3
+; CI-NEXT: s_mov_b32 s6, 3
+; CI-NEXT: s_mov_b32 s7, 0
+; CI-NEXT: s_waitcnt vmcnt(0)
+; CI-NEXT: v_cvt_f32_f16_e32 v2, v0
+; CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v3, v0
+; CI-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; CI-NEXT: v_cvt_f32_f16_e32 v4, v1
+; CI-NEXT: v_cvt_f32_f16_e32 v5, v0
+; CI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0 offset:32
+; CI-NEXT: s_waitcnt vmcnt(0)
+; CI-NEXT: v_cvt_f32_f16_e32 v7, v1
+; CI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; CI-NEXT: v_cvt_f32_f16_e32 v6, v0
+; CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_div_scale_f32 v9, s[4:5], v1, v1, v5
+; CI-NEXT: v_div_scale_f32 v8, vcc, v5, v1, v5
+; CI-NEXT: v_rcp_f32_e32 v10, v9
+; CI-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
+; CI-NEXT: v_fma_f32 v11, -v9, v10, 1.0
+; CI-NEXT: v_fma_f32 v10, v11, v10, v10
+; CI-NEXT: v_mul_f32_e32 v11, v8, v10
+; CI-NEXT: v_fma_f32 v12, -v9, v11, v8
+; CI-NEXT: v_fma_f32 v11, v12, v10, v11
+; CI-NEXT: v_fma_f32 v8, -v9, v11, v8
+; CI-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
+; CI-NEXT: v_div_fmas_f32 v8, v8, v10, v11
+; CI-NEXT: v_div_fixup_f32 v8, v8, v1, v5
+; CI-NEXT: v_trunc_f32_e32 v8, v8
+; CI-NEXT: v_fma_f32 v1, -v8, v1, v5
+; CI-NEXT: v_div_scale_f32 v8, s[4:5], v7, v7, v4
+; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
+; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; CI-NEXT: v_div_scale_f32 v5, vcc, v4, v7, v4
+; CI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; CI-NEXT: v_rcp_f32_e32 v9, v8
+; CI-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
+; CI-NEXT: v_fma_f32 v10, -v8, v9, 1.0
+; CI-NEXT: v_fma_f32 v9, v10, v9, v9
+; CI-NEXT: v_mul_f32_e32 v10, v5, v9
+; CI-NEXT: v_fma_f32 v11, -v8, v10, v5
+; CI-NEXT: v_fma_f32 v10, v11, v9, v10
+; CI-NEXT: v_fma_f32 v5, -v8, v10, v5
+; CI-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
+; CI-NEXT: v_div_fmas_f32 v5, v5, v9, v10
+; CI-NEXT: v_div_fixup_f32 v5, v5, v7, v4
+; CI-NEXT: v_trunc_f32_e32 v5, v5
+; CI-NEXT: v_fma_f32 v4, -v5, v7, v4
+; CI-NEXT: v_div_scale_f32 v5, s[4:5], v0, v0, v3
+; CI-NEXT: v_cvt_f16_f32_e32 v4, v4
+; CI-NEXT: v_or_b32_e32 v1, v4, v1
+; CI-NEXT: v_div_scale_f32 v4, vcc, v3, v0, v3
+; CI-NEXT: v_rcp_f32_e32 v7, v5
+; CI-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
+; CI-NEXT: v_fma_f32 v8, -v5, v7, 1.0
+; CI-NEXT: v_fma_f32 v7, v8, v7, v7
+; CI-NEXT: v_mul_f32_e32 v8, v4, v7
+; CI-NEXT: v_fma_f32 v9, -v5, v8, v4
+; CI-NEXT: v_fma_f32 v8, v9, v7, v8
+; CI-NEXT: v_fma_f32 v4, -v5, v8, v4
+; CI-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
+; CI-NEXT: v_div_fmas_f32 v4, v4, v7, v8
+; CI-NEXT: v_div_fixup_f32 v4, v4, v0, v3
+; CI-NEXT: v_trunc_f32_e32 v4, v4
+; CI-NEXT: v_fma_f32 v0, -v4, v0, v3
+; CI-NEXT: v_div_scale_f32 v4, s[4:5], v6, v6, v2
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; CI-NEXT: v_div_scale_f32 v3, vcc, v2, v6, v2
+; CI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; CI-NEXT: v_rcp_f32_e32 v5, v4
+; CI-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
+; CI-NEXT: v_fma_f32 v7, -v4, v5, 1.0
+; CI-NEXT: v_fma_f32 v5, v7, v5, v5
+; CI-NEXT: v_mul_f32_e32 v7, v3, v5
+; CI-NEXT: v_fma_f32 v8, -v4, v7, v3
+; CI-NEXT: v_fma_f32 v7, v8, v5, v7
+; CI-NEXT: v_fma_f32 v3, -v4, v7, v3
+; CI-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
+; CI-NEXT: v_div_fmas_f32 v3, v3, v5, v7
+; CI-NEXT: v_div_fixup_f32 v3, v3, v6, v2
+; CI-NEXT: v_trunc_f32_e32 v3, v3
+; CI-NEXT: v_fma_f32 v2, -v3, v6, v2
+; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; CI-NEXT: v_or_b32_e32 v0, v2, v0
+; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; CI-NEXT: s_endpgm
+;
+; VI-LABEL: frem_v4f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v2, s6
+; VI-NEXT: s_add_u32 s0, s0, 32
+; VI-NEXT: s_addc_u32 s1, s1, 0
+; VI-NEXT: v_mov_b32_e32 v5, s1
+; VI-NEXT: v_mov_b32_e32 v4, s0
+; VI-NEXT: flat_load_dwordx2 v[4:5], v[4:5]
+; VI-NEXT: v_mov_b32_e32 v3, s7
+; VI-NEXT: flat_load_dwordx2 v[2:3], v[2:3]
+; VI-NEXT: v_mov_b32_e32 v0, s4
+; VI-NEXT: v_mov_b32_e32 v1, s5
+; VI-NEXT: s_waitcnt vmcnt(1) lgkmcnt(1)
+; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v5
+; VI-NEXT: v_cvt_f32_f16_e32 v9, v8
+; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v3
+; VI-NEXT: v_cvt_f32_f16_e32 v7, v6
+; VI-NEXT: v_rcp_f32_e32 v9, v9
+; VI-NEXT: v_mul_f32_e32 v7, v7, v9
+; VI-NEXT: v_cvt_f16_f32_e32 v7, v7
+; VI-NEXT: v_div_fixup_f16 v7, v7, v8, v6
+; VI-NEXT: v_trunc_f16_e32 v7, v7
+; VI-NEXT: v_fma_f16 v6, -v7, v8, v6
+; VI-NEXT: v_cvt_f32_f16_e32 v8, v5
+; VI-NEXT: v_cvt_f32_f16_e32 v7, v3
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; VI-NEXT: v_rcp_f32_e32 v8, v8
+; VI-NEXT: v_mul_f32_e32 v7, v7, v8
+; VI-NEXT: v_cvt_f16_f32_e32 v7, v7
+; VI-NEXT: v_div_fixup_f16 v7, v7, v5, v3
+; VI-NEXT: v_trunc_f16_e32 v7, v7
+; VI-NEXT: v_fma_f16 v3, -v7, v5, v3
+; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v4
+; VI-NEXT: v_cvt_f32_f16_e32 v8, v7
+; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; VI-NEXT: v_or_b32_e32 v3, v3, v6
+; VI-NEXT: v_cvt_f32_f16_e32 v6, v5
+; VI-NEXT: v_rcp_f32_e32 v8, v8
+; VI-NEXT: v_mul_f32_e32 v6, v6, v8
+; VI-NEXT: v_cvt_f16_f32_e32 v6, v6
+; VI-NEXT: v_div_fixup_f16 v6, v6, v7, v5
+; VI-NEXT: v_trunc_f16_e32 v6, v6
+; VI-NEXT: v_fma_f16 v5, -v6, v7, v5
+; VI-NEXT: v_cvt_f32_f16_e32 v7, v4
+; VI-NEXT: v_cvt_f32_f16_e32 v6, v2
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; VI-NEXT: v_rcp_f32_e32 v7, v7
+; VI-NEXT: v_mul_f32_e32 v6, v6, v7
+; VI-NEXT: v_cvt_f16_f32_e32 v6, v6
+; VI-NEXT: v_div_fixup_f16 v6, v6, v4, v2
+; VI-NEXT: v_trunc_f16_e32 v6, v6
+; VI-NEXT: v_fma_f16 v2, -v6, v4, v2
+; VI-NEXT: v_or_b32_e32 v2, v2, v5
+; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; VI-NEXT: s_endpgm
+ <4 x half> addrspace(1)* %in2) #0 {
+ %gep2 = getelementptr <4 x half>, <4 x half> addrspace(1)* %in2, i32 4
+ %r0 = load <4 x half>, <4 x half> addrspace(1)* %in1, align 16
+ %r1 = load <4 x half>, <4 x half> addrspace(1)* %gep2, align 16
+ %r2 = frem <4 x half> %r0, %r1
+ store <4 x half> %r2, <4 x half> addrspace(1)* %out, align 16
+ ret void
+}
+
define amdgpu_kernel void @frem_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in1,
; SI-LABEL: frem_v2f32:
; SI: ; %bb.0:
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