[PATCH] D84653: ARM: make Thumb1 instructions non-flag-setting in IT block.

[Tim Northover via Phabricator via llvm-commits]

t.p.northover created this revision.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls, mcrosier.
Herald added a project: LLVM.

Many Thumb1 instructions are defined to set CPSR if executed outside an IT block, but leave it alone from inside one. In MachineIR this is represented by whether an optional register is CPSR or NoReg (0), and affects how the instructions are printed.

This sets the instruction to the appropriate form during if-conversion.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D84653

Files:
  llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/lib/Target/ARM/ARMInstrFormats.td
  llvm/test/CodeGen/Thumb2/ifcvt-rescan-diamonds.ll


Index: llvm/test/CodeGen/Thumb2/ifcvt-rescan-diamonds.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/ifcvt-rescan-diamonds.ll
+++ llvm/test/CodeGen/Thumb2/ifcvt-rescan-diamonds.ll
@@ -22,7 +22,8 @@
 ; CHECK-NEXT: it eq
 ; CHECK-NEXT: ldreq
 ; CHECK-NEXT: it ne
-; CHECK-NEXT: movsne
+  ; N.b. 16-bit mov instruction in IT block does not set flags.
+; CHECK-NEXT: movne
 ; CHECK-NEXT: mvns
 ; CHECK-NEXT: b
 cond.true77:                                      ; preds = %while.cond38
Index: llvm/lib/Target/ARM/ARMInstrFormats.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrFormats.td
+++ llvm/lib/Target/ARM/ARMInstrFormats.td
@@ -403,8 +403,9 @@
   bit isUnaryDataProc = 0;
   bit canXformTo16Bit = 0;
   // The instruction is a 16-bit flag setting Thumb instruction. Used
-  // by the parser to determine whether to require the 'S' suffix on the
-  // mnemonic (when not in an IT block) or preclude it (when in an IT block).
+  // by the parser and if-converter to determine whether to require the 'S'
+  // suffix on the mnemonic (when not in an IT block) or preclude it (when
+  // in an IT block).
   bit thumbArithFlagSetting = 0;
 
   bit validForTailPredication = 0;
Index: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -537,6 +537,24 @@
     MachineOperand &PMO = MI.getOperand(PIdx);
     PMO.setImm(Pred[0].getImm());
     MI.getOperand(PIdx+1).setReg(Pred[1].getReg());
+
+    // Thumb 1 arithmetic instructions do not set CPSR when executed inside an
+    // IT block. This affects how they are printed.
+    const MCInstrDesc &MCID = MI.getDesc();
+    if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
+      // Find the optional-def operand (cc_out).
+      unsigned OpNo;
+      for (OpNo = 0;
+           !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
+           ++OpNo)
+        ;
+      assert(MCID.OpInfo[OpNo].isOptionalDef());
+      assert((MI.getOperand(OpNo).isDead() ||
+              MI.getOperand(OpNo).getReg() != ARM::CPSR) &&
+             "if conversion tried to stop defining used CPSR");
+      MI.getOperand(OpNo).setReg(ARM::NoRegister);
+    }
+
     return true;
   }
   return false;


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