[llvm] bd20680 - [PowerPC] Split s34imm into two types
Eric Christopher via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 9 13:40:31 PDT 2020
Hi Kamau and Stefan,
This was failing with asserts in a release+asserts build so I've reverted
it thusly:
echristo at athyra ~/s/llvm-project> git push
To github.com:llvm/llvm-project.git
c025bdf25a5..ce1e4853b5a master -> master
if you need any help reproducing or debugging let me know :)
Thanks!
-eric
On Thu, Jul 9, 2020 at 9:29 AM Kamau Bridgeman via llvm-commits <
llvm-commits at lists.llvm.org> wrote:
>
> Author: Stefan Pintilie
> Date: 2020-07-09T11:28:32-05:00
> New Revision: bd2068031121adf5a0e28d9306a1741d6f0bbd87
>
> URL:
> https://github.com/llvm/llvm-project/commit/bd2068031121adf5a0e28d9306a1741d6f0bbd87
> DIFF:
> https://github.com/llvm/llvm-project/commit/bd2068031121adf5a0e28d9306a1741d6f0bbd87.diff
>
> LOG: [PowerPC] Split s34imm into two types
>
> Currently the instruction paddi always takes s34imm as the type for the
> 34 bit immediate. However, the PC Relative form of the instruction should
> not produce the same fixup as the non PC Relative form.
> This patch splits the s34imm type into s34imm and s34imm_pcrel so that two
> different fixups can be emitted.
>
> Reviewed By: kamaub, nemanjai
>
> Differential Revision: https://reviews.llvm.org/D83255
>
> Added:
> llvm/test/MC/PowerPC/ppc64-errors-emit-obj.s
>
> Modified:
> llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
> llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
> llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h
> llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
> llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h
> llvm/lib/Target/PowerPC/PPCInstrInfo.td
> llvm/lib/Target/PowerPC/PPCInstrPrefix.td
>
> Removed:
>
>
>
>
> ################################################################################
> diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
> b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
> index dbaf221db9fc..59cb2b994a4b 100644
> --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
> +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
> @@ -46,6 +46,7 @@ static uint64_t adjustFixupValue(unsigned Kind, uint64_t
> Value) {
> case PPC::fixup_ppc_half16ds:
> return Value & 0xfffc;
> case PPC::fixup_ppc_pcrel34:
> + case PPC::fixup_ppc_imm34:
> return Value & 0x3ffffffff;
> }
> }
> @@ -68,6 +69,7 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
> case PPC::fixup_ppc_br24_notoc:
> return 4;
> case PPC::fixup_ppc_pcrel34:
> + case PPC::fixup_ppc_imm34:
> case FK_Data_8:
> return 8;
> case PPC::fixup_ppc_nofixup:
> @@ -100,6 +102,7 @@ class PPCAsmBackend : public MCAsmBackend {
> { "fixup_ppc_half16", 0, 16, 0 },
> { "fixup_ppc_half16ds", 0, 14, 0 },
> { "fixup_ppc_pcrel34", 0, 34,
> MCFixupKindInfo::FKF_IsPCRel },
> + { "fixup_ppc_imm34", 0, 34, 0 },
> { "fixup_ppc_nofixup", 0, 0, 0 }
> };
> const static MCFixupKindInfo InfosLE[PPC::NumTargetFixupKinds] = {
> @@ -112,6 +115,7 @@ class PPCAsmBackend : public MCAsmBackend {
> { "fixup_ppc_half16", 0, 16, 0 },
> { "fixup_ppc_half16ds", 2, 14, 0 },
> { "fixup_ppc_pcrel34", 0, 34,
> MCFixupKindInfo::FKF_IsPCRel },
> + { "fixup_ppc_imm34", 0, 34, 0 },
> { "fixup_ppc_nofixup", 0, 0, 0 }
> };
>
>
> diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
> b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
> index d8b3301e97f1..1af08ec5539d 100644
> --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
> +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
> @@ -409,6 +409,9 @@ unsigned PPCELFObjectWriter::getRelocType(MCContext
> &Ctx, const MCValue &Target,
> break;
> }
> break;
> + case PPC::fixup_ppc_imm34:
> + llvm_unreachable("Unsupported Modifier for fixup_ppc_imm34.");
> + break;
> case FK_Data_8:
> switch (Modifier) {
> default: llvm_unreachable("Unsupported Modifier");
>
> diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h
> b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h
> index 2fb8947fd4e0..73292f7b7938 100644
> --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h
> +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h
> @@ -43,6 +43,9 @@ enum Fixups {
> // A 34-bit fixup corresponding to PC-relative paddi.
> fixup_ppc_pcrel34,
>
> + // A 34-bit fixup corresponding to Non-PC-relative paddi.
> + fixup_ppc_imm34,
> +
> /// Not a true fixup, but ties a symbol to a call to __tls_get_addr for
> the
> /// TLS general and local dynamic models, or inserts the thread-pointer
> /// register number.
>
> diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
> b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
> index fb65e7320f2b..8c0e0a80b1e2 100644
> --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
> +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
> @@ -104,20 +104,36 @@ unsigned PPCMCCodeEmitter::getImm16Encoding(const
> MCInst &MI, unsigned OpNo,
> return 0;
> }
>
> -uint64_t
> -PPCMCCodeEmitter::getImm34Encoding(const MCInst &MI, unsigned OpNo,
> - SmallVectorImpl<MCFixup> &Fixups,
> - const MCSubtargetInfo &STI) const {
> +uint64_t PPCMCCodeEmitter::getImm34Encoding(const MCInst &MI, unsigned
> OpNo,
> + SmallVectorImpl<MCFixup>
> &Fixups,
> + const MCSubtargetInfo &STI,
> + MCFixupKind Fixup) const {
> const MCOperand &MO = MI.getOperand(OpNo);
> - if (MO.isReg() || MO.isImm())
> + assert(!MO.isReg() && "Not expecting a register for this operand.");
> + if (MO.isImm())
> return getMachineOpValue(MI, MO, Fixups, STI);
>
> // Add a fixup for the immediate field.
> - Fixups.push_back(MCFixup::create(0, MO.getExpr(),
> - (MCFixupKind)PPC::fixup_ppc_pcrel34));
> + Fixups.push_back(MCFixup::create(0, MO.getExpr(), Fixup));
> return 0;
> }
>
> +uint64_t
> +PPCMCCodeEmitter::getImm34EncodingNoPCRel(const MCInst &MI, unsigned OpNo,
> + SmallVectorImpl<MCFixup>
> &Fixups,
> + const MCSubtargetInfo &STI)
> const {
> + return getImm34Encoding(MI, OpNo, Fixups, STI,
> + (MCFixupKind)PPC::fixup_ppc_imm34);
> +}
> +
> +uint64_t
> +PPCMCCodeEmitter::getImm34EncodingPCRel(const MCInst &MI, unsigned OpNo,
> + SmallVectorImpl<MCFixup> &Fixups,
> + const MCSubtargetInfo &STI) const
> {
> + return getImm34Encoding(MI, OpNo, Fixups, STI,
> + (MCFixupKind)PPC::fixup_ppc_pcrel34);
> +}
> +
> unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned
> OpNo,
> SmallVectorImpl<MCFixup>
> &Fixups,
> const MCSubtargetInfo &STI)
> const {
>
> diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h
> b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h
> index 588aa76bd806..4504cc6a7405 100644
> --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h
> +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h
> @@ -52,7 +52,14 @@ class PPCMCCodeEmitter : public MCCodeEmitter {
> const MCSubtargetInfo &STI) const;
> uint64_t getImm34Encoding(const MCInst &MI, unsigned OpNo,
> SmallVectorImpl<MCFixup> &Fixups,
> - const MCSubtargetInfo &STI) const;
> + const MCSubtargetInfo &STI,
> + MCFixupKind Fixup) const;
> + uint64_t getImm34EncodingNoPCRel(const MCInst &MI, unsigned OpNo,
> + SmallVectorImpl<MCFixup> &Fixups,
> + const MCSubtargetInfo &STI) const;
> + uint64_t getImm34EncodingPCRel(const MCInst &MI, unsigned OpNo,
> + SmallVectorImpl<MCFixup> &Fixups,
> + const MCSubtargetInfo &STI) const;
> unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
> SmallVectorImpl<MCFixup> &Fixups,
> const MCSubtargetInfo &STI) const;
>
> diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
> b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
> index 673ab63039cf..39a90bf9b346 100644
> --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
> +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
> @@ -757,7 +757,13 @@ def PPCS34ImmAsmOperand : AsmOperandClass {
> }
> def s34imm : Operand<i64> {
> let PrintMethod = "printS34ImmOperand";
> - let EncoderMethod = "getImm34Encoding";
> + let EncoderMethod = "getImm34EncodingNoPCRel";
> + let ParserMatchClass = PPCS34ImmAsmOperand;
> + let DecoderMethod = "decodeSImmOperand<34>";
> +}
> +def s34imm_pcrel : Operand<i64> {
> + let PrintMethod = "printS34ImmOperand";
> + let EncoderMethod = "getImm34EncodingPCRel";
> let ParserMatchClass = PPCS34ImmAsmOperand;
> let DecoderMethod = "decodeSImmOperand<34>";
> }
>
> diff --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
> b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
> index 2c21d0a175ad..91bb912e5726 100644
> --- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
> +++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
> @@ -432,7 +432,7 @@ let Predicates = [PrefixInstrs] in {
> let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
> defm PADDI8 :
> MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc:$RA,
> s34imm:$SI),
> - (ins immZero:$RA, s34imm:$SI),
> + (ins immZero:$RA, s34imm_pcrel:$SI),
> "paddi $RT, $RA, $SI", IIC_LdStLFD>;
> let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
> def PLI8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT),
> @@ -442,7 +442,7 @@ let Predicates = [PrefixInstrs] in {
> }
> defm PADDI :
> MLS_DForm_R_SI34_RTA5_p<14, (outs gprc:$RT), (ins gprc:$RA,
> s34imm:$SI),
> - (ins immZero:$RA, s34imm:$SI),
> + (ins immZero:$RA, s34imm_pcrel:$SI),
> "paddi $RT, $RA, $SI", IIC_LdStLFD>;
> let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
> def PLI : MLS_DForm_SI34_RT5<14, (outs gprc:$RT),
>
> diff --git a/llvm/test/MC/PowerPC/ppc64-errors-emit-obj.s
> b/llvm/test/MC/PowerPC/ppc64-errors-emit-obj.s
> new file mode 100644
> index 000000000000..0d2c879380e0
> --- /dev/null
> +++ b/llvm/test/MC/PowerPC/ppc64-errors-emit-obj.s
> @@ -0,0 +1,7 @@
> +# RUN: not --crash llvm-mc -triple powerpc64-- --filetype=obj < %s 2> %t
> +# RUN: FileCheck < %t %s
> +# RUN: not --crash llvm-mc -triple powerpc64le-- --filetype=obj < %s 2> %t
> +# RUN: FileCheck < %t %s
> +
> +# CHECK: Unsupported Modifier for fixup_ppc_imm34.
> +paddi 3, 13, symbol at toc, 0
>
>
>
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