<div dir="ltr">Hi Kamau and Stefan,<div><br></div><div>This was failing with asserts in a release+asserts build so I've reverted it thusly:</div><div><br></div><div>echristo@athyra ~/s/llvm-project> git push<br>To github.com:llvm/llvm-project.git<br> c025bdf25a5..ce1e4853b5a master -> master<br></div><div><br></div><div>if you need any help reproducing or debugging let me know :)</div><div><br></div><div>Thanks!</div><div><br></div><div>-eric</div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, Jul 9, 2020 at 9:29 AM Kamau Bridgeman via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><br>
Author: Stefan Pintilie<br>
Date: 2020-07-09T11:28:32-05:00<br>
New Revision: bd2068031121adf5a0e28d9306a1741d6f0bbd87<br>
<br>
URL: <a href="https://github.com/llvm/llvm-project/commit/bd2068031121adf5a0e28d9306a1741d6f0bbd87" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/bd2068031121adf5a0e28d9306a1741d6f0bbd87</a><br>
DIFF: <a href="https://github.com/llvm/llvm-project/commit/bd2068031121adf5a0e28d9306a1741d6f0bbd87.diff" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/bd2068031121adf5a0e28d9306a1741d6f0bbd87.diff</a><br>
<br>
LOG: [PowerPC] Split s34imm into two types<br>
<br>
Currently the instruction paddi always takes s34imm as the type for the<br>
34 bit immediate. However, the PC Relative form of the instruction should<br>
not produce the same fixup as the non PC Relative form.<br>
This patch splits the s34imm type into s34imm and s34imm_pcrel so that two<br>
different fixups can be emitted.<br>
<br>
Reviewed By: kamaub, nemanjai<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D83255" rel="noreferrer" target="_blank">https://reviews.llvm.org/D83255</a><br>
<br>
Added: <br>
llvm/test/MC/PowerPC/ppc64-errors-emit-obj.s<br>
<br>
Modified: <br>
llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp<br>
llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp<br>
llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h<br>
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp<br>
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h<br>
llvm/lib/Target/PowerPC/PPCInstrInfo.td<br>
llvm/lib/Target/PowerPC/PPCInstrPrefix.td<br>
<br>
Removed: <br>
<br>
<br>
<br>
################################################################################<br>
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp<br>
index dbaf221db9fc..59cb2b994a4b 100644<br>
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp<br>
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp<br>
@@ -46,6 +46,7 @@ static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) {<br>
case PPC::fixup_ppc_half16ds:<br>
return Value & 0xfffc;<br>
case PPC::fixup_ppc_pcrel34:<br>
+ case PPC::fixup_ppc_imm34:<br>
return Value & 0x3ffffffff;<br>
}<br>
}<br>
@@ -68,6 +69,7 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {<br>
case PPC::fixup_ppc_br24_notoc:<br>
return 4;<br>
case PPC::fixup_ppc_pcrel34:<br>
+ case PPC::fixup_ppc_imm34:<br>
case FK_Data_8:<br>
return 8;<br>
case PPC::fixup_ppc_nofixup:<br>
@@ -100,6 +102,7 @@ class PPCAsmBackend : public MCAsmBackend {<br>
{ "fixup_ppc_half16", 0, 16, 0 },<br>
{ "fixup_ppc_half16ds", 0, 14, 0 },<br>
{ "fixup_ppc_pcrel34", 0, 34, MCFixupKindInfo::FKF_IsPCRel },<br>
+ { "fixup_ppc_imm34", 0, 34, 0 },<br>
{ "fixup_ppc_nofixup", 0, 0, 0 }<br>
};<br>
const static MCFixupKindInfo InfosLE[PPC::NumTargetFixupKinds] = {<br>
@@ -112,6 +115,7 @@ class PPCAsmBackend : public MCAsmBackend {<br>
{ "fixup_ppc_half16", 0, 16, 0 },<br>
{ "fixup_ppc_half16ds", 2, 14, 0 },<br>
{ "fixup_ppc_pcrel34", 0, 34, MCFixupKindInfo::FKF_IsPCRel },<br>
+ { "fixup_ppc_imm34", 0, 34, 0 },<br>
{ "fixup_ppc_nofixup", 0, 0, 0 }<br>
};<br>
<br>
<br>
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp<br>
index d8b3301e97f1..1af08ec5539d 100644<br>
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp<br>
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp<br>
@@ -409,6 +409,9 @@ unsigned PPCELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target,<br>
break;<br>
}<br>
break;<br>
+ case PPC::fixup_ppc_imm34:<br>
+ llvm_unreachable("Unsupported Modifier for fixup_ppc_imm34.");<br>
+ break;<br>
case FK_Data_8:<br>
switch (Modifier) {<br>
default: llvm_unreachable("Unsupported Modifier");<br>
<br>
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h<br>
index 2fb8947fd4e0..73292f7b7938 100644<br>
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h<br>
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h<br>
@@ -43,6 +43,9 @@ enum Fixups {<br>
// A 34-bit fixup corresponding to PC-relative paddi.<br>
fixup_ppc_pcrel34,<br>
<br>
+ // A 34-bit fixup corresponding to Non-PC-relative paddi.<br>
+ fixup_ppc_imm34,<br>
+<br>
/// Not a true fixup, but ties a symbol to a call to __tls_get_addr for the<br>
/// TLS general and local dynamic models, or inserts the thread-pointer<br>
/// register number.<br>
<br>
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp<br>
index fb65e7320f2b..8c0e0a80b1e2 100644<br>
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp<br>
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp<br>
@@ -104,20 +104,36 @@ unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,<br>
return 0;<br>
}<br>
<br>
-uint64_t<br>
-PPCMCCodeEmitter::getImm34Encoding(const MCInst &MI, unsigned OpNo,<br>
- SmallVectorImpl<MCFixup> &Fixups,<br>
- const MCSubtargetInfo &STI) const {<br>
+uint64_t PPCMCCodeEmitter::getImm34Encoding(const MCInst &MI, unsigned OpNo,<br>
+ SmallVectorImpl<MCFixup> &Fixups,<br>
+ const MCSubtargetInfo &STI,<br>
+ MCFixupKind Fixup) const {<br>
const MCOperand &MO = MI.getOperand(OpNo);<br>
- if (MO.isReg() || MO.isImm())<br>
+ assert(!MO.isReg() && "Not expecting a register for this operand.");<br>
+ if (MO.isImm())<br>
return getMachineOpValue(MI, MO, Fixups, STI);<br>
<br>
// Add a fixup for the immediate field.<br>
- Fixups.push_back(MCFixup::create(0, MO.getExpr(),<br>
- (MCFixupKind)PPC::fixup_ppc_pcrel34));<br>
+ Fixups.push_back(MCFixup::create(0, MO.getExpr(), Fixup));<br>
return 0;<br>
}<br>
<br>
+uint64_t<br>
+PPCMCCodeEmitter::getImm34EncodingNoPCRel(const MCInst &MI, unsigned OpNo,<br>
+ SmallVectorImpl<MCFixup> &Fixups,<br>
+ const MCSubtargetInfo &STI) const {<br>
+ return getImm34Encoding(MI, OpNo, Fixups, STI,<br>
+ (MCFixupKind)PPC::fixup_ppc_imm34);<br>
+}<br>
+<br>
+uint64_t<br>
+PPCMCCodeEmitter::getImm34EncodingPCRel(const MCInst &MI, unsigned OpNo,<br>
+ SmallVectorImpl<MCFixup> &Fixups,<br>
+ const MCSubtargetInfo &STI) const {<br>
+ return getImm34Encoding(MI, OpNo, Fixups, STI,<br>
+ (MCFixupKind)PPC::fixup_ppc_pcrel34);<br>
+}<br>
+<br>
unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,<br>
SmallVectorImpl<MCFixup> &Fixups,<br>
const MCSubtargetInfo &STI) const {<br>
<br>
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h<br>
index 588aa76bd806..4504cc6a7405 100644<br>
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h<br>
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h<br>
@@ -52,7 +52,14 @@ class PPCMCCodeEmitter : public MCCodeEmitter {<br>
const MCSubtargetInfo &STI) const;<br>
uint64_t getImm34Encoding(const MCInst &MI, unsigned OpNo,<br>
SmallVectorImpl<MCFixup> &Fixups,<br>
- const MCSubtargetInfo &STI) const;<br>
+ const MCSubtargetInfo &STI,<br>
+ MCFixupKind Fixup) const;<br>
+ uint64_t getImm34EncodingNoPCRel(const MCInst &MI, unsigned OpNo,<br>
+ SmallVectorImpl<MCFixup> &Fixups,<br>
+ const MCSubtargetInfo &STI) const;<br>
+ uint64_t getImm34EncodingPCRel(const MCInst &MI, unsigned OpNo,<br>
+ SmallVectorImpl<MCFixup> &Fixups,<br>
+ const MCSubtargetInfo &STI) const;<br>
unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,<br>
SmallVectorImpl<MCFixup> &Fixups,<br>
const MCSubtargetInfo &STI) const;<br>
<br>
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td<br>
index 673ab63039cf..39a90bf9b346 100644<br>
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td<br>
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td<br>
@@ -757,7 +757,13 @@ def PPCS34ImmAsmOperand : AsmOperandClass {<br>
}<br>
def s34imm : Operand<i64> {<br>
let PrintMethod = "printS34ImmOperand";<br>
- let EncoderMethod = "getImm34Encoding";<br>
+ let EncoderMethod = "getImm34EncodingNoPCRel";<br>
+ let ParserMatchClass = PPCS34ImmAsmOperand;<br>
+ let DecoderMethod = "decodeSImmOperand<34>";<br>
+}<br>
+def s34imm_pcrel : Operand<i64> {<br>
+ let PrintMethod = "printS34ImmOperand";<br>
+ let EncoderMethod = "getImm34EncodingPCRel";<br>
let ParserMatchClass = PPCS34ImmAsmOperand;<br>
let DecoderMethod = "decodeSImmOperand<34>";<br>
}<br>
<br>
diff --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td<br>
index 2c21d0a175ad..91bb912e5726 100644<br>
--- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td<br>
+++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td<br>
@@ -432,7 +432,7 @@ let Predicates = [PrefixInstrs] in {<br>
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {<br>
defm PADDI8 :<br>
MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc:$RA, s34imm:$SI),<br>
- (ins immZero:$RA, s34imm:$SI),<br>
+ (ins immZero:$RA, s34imm_pcrel:$SI),<br>
"paddi $RT, $RA, $SI", IIC_LdStLFD>;<br>
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {<br>
def PLI8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT),<br>
@@ -442,7 +442,7 @@ let Predicates = [PrefixInstrs] in {<br>
}<br>
defm PADDI :<br>
MLS_DForm_R_SI34_RTA5_p<14, (outs gprc:$RT), (ins gprc:$RA, s34imm:$SI),<br>
- (ins immZero:$RA, s34imm:$SI),<br>
+ (ins immZero:$RA, s34imm_pcrel:$SI),<br>
"paddi $RT, $RA, $SI", IIC_LdStLFD>;<br>
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {<br>
def PLI : MLS_DForm_SI34_RT5<14, (outs gprc:$RT),<br>
<br>
diff --git a/llvm/test/MC/PowerPC/ppc64-errors-emit-obj.s b/llvm/test/MC/PowerPC/ppc64-errors-emit-obj.s<br>
new file mode 100644<br>
index 000000000000..0d2c879380e0<br>
--- /dev/null<br>
+++ b/llvm/test/MC/PowerPC/ppc64-errors-emit-obj.s<br>
@@ -0,0 +1,7 @@<br>
+# RUN: not --crash llvm-mc -triple powerpc64-- --filetype=obj < %s 2> %t<br>
+# RUN: FileCheck < %t %s<br>
+# RUN: not --crash llvm-mc -triple powerpc64le-- --filetype=obj < %s 2> %t<br>
+# RUN: FileCheck < %t %s<br>
+<br>
+# CHECK: Unsupported Modifier for fixup_ppc_imm34.<br>
+paddi 3, 13, symbol@toc, 0<br>
<br>
<br>
<br>
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</blockquote></div>