[PATCH] D83466: [PowerPC] Exploit type-J min/max for maximum/minimum intrinsic

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf created this revision.
qiucf added reviewers: PowerPC, hfinkel, nemanjai, jsji, steven.zhang.
Herald added subscribers: llvm-commits, shchenz, kbarton, hiraditya.
Herald added a project: LLVM.

According to LangRef, LLVM have `llvm.minimum.*` and `llvm.maximum.*` intrinsics introduced in D52764 <https://reviews.llvm.org/D52764>. (besides `llvm.maxnum.*` and `llvm.minnum.*`)

Its semantics is (taking minimum as example):

> If either operand is a NaN, returns NaN. Otherwise returns the lesser of the two arguments. -0.0 is considered to be less than +0.0 for this intrinsic. Note that these are the semantics specified in the draft of IEEE 754-2018.

PowerPC has type-j max/min instruction (`xs(max|min)jdp`) since ISA 3.0, the semantics is:

> If src1 or src2 is a SNaN, an Invalid Operation exception occurs.
> 
> If src1 is a NaN, result is src1. Otherwise, if src2 is a NaN, result is src2.
> 
> Otherwise, if src1 is a Zero and src2 is a Zero and either src1 or src2 is a -Zero, the result is -Zero.
> 
> Otherwise, if src1 is a +Zero and src2 is a +Zero, the result is +Zero.
> 
> Otherwise, if src1 is less than src2, result is src1. Otherwise, result is src2.

This instruction returns the 'first' that is NaN, and respects zero signs.

One thing in confusion is whether `llvm.fmaximum.*` should quiet it if result is SNaN.. This instruction won't.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D83466

Files:
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/fminmax-type-j.ll


Index: llvm/test/CodeGen/PowerPC/fminmax-type-j.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/fminmax-type-j.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+declare double @llvm.maximum.f64(double, double)
+declare double @llvm.minimum.f64(double, double)
+
+define double @test_max(double %a, double %b) {
+; CHECK-LABEL: test_max:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xsmaxjdp 1, 1, 2
+; CHECK-NEXT:    blr
+entry:
+  %0 = call double @llvm.maximum.f64(double %a, double %b)
+  ret double %0
+}
+
+define double @test_min(double %a, double %b) {
+; CHECK-LABEL: test_min:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xsminjdp 1, 1, 2
+; CHECK-NEXT:    blr
+entry:
+  %0 = call double @llvm.minimum.f64(double %a, double %b)
+  ret double %0
+}
+
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -1616,10 +1616,12 @@
 
   // FIXME: Setting the hasSideEffects flag here to match current behaviour.
   let hasSideEffects = 1 in {
-    def XSMAXJDP : XX3_XT5_XA5_XB5<60, 144, "xsmaxjdp", vsrc, vsfrc, vsfrc,
-                                   IIC_VecFP, []>;
-    def XSMINJDP : XX3_XT5_XA5_XB5<60, 152, "xsminjdp", vsrc, vsfrc, vsfrc,
-                                   IIC_VecFP, []>;
+    def XSMAXJDP : XX3_XT5_XA5_XB5<60, 144, "xsmaxjdp", vsfrc, vsfrc, vsfrc,
+                                   IIC_VecFP,
+                                   [(set f64:$XT, (fmaximum f64:$XA, f64:$XB))]>;
+    def XSMINJDP : XX3_XT5_XA5_XB5<60, 152, "xsminjdp", vsfrc, vsfrc, vsfrc,
+                                   IIC_VecFP,
+                                   [(set f64:$XT, (fminimum f64:$XA, f64:$XB))]>;
   }
 
   // Vector Byte-Reverse H/W/D/Q Word


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