[PATCH] D83052: [PowerPC][Power10] Add Vector Insert Instruction Definitions and MC Tests

[Lei Huang via Phabricator via llvm-commits]

lei requested changes to this revision.
lei added inline comments.
This revision now requires changes to proceed.


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Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:231
+// "/ UIM" (unused bit followed by a 4-bit immediate)
+class VX_VRT5_UIM5_RB5<bits<11> xo, string opc, list<dag> pattern>
+  : VXForm_1<xo, (outs vrrc:$VRT), (ins vrrc:$VRTi, u4imm:$UIM, g8rc:$RB),
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Was this meant to be `VXForm_VRT5_UIM5_RB5`?


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Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:764
+  def VINSD : VX_VRT5_UIM5_RB5<463, "vinsd", []>;
+  def VINSBVLX : VXForm_1<15, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA,
+                          vrrc:$vB), "vinsbvlx $vD, $rA, $vB", IIC_VecGeneral,
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Why not define a class similar to `VX_VRT5_UIM5_RB5` to be used for the instruction def below?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83052/new/

https://reviews.llvm.org/D83052