[PATCH] D83052: [PowerPC][Power10] Add Vector Insert Instruction Definitions and MC Tests

[Amy Kwan via Phabricator via llvm-commits]

amyk created this revision.
amyk added reviewers: power-llvm-team, PowerPC, nemanjai, lei, biplmish.
amyk added projects: LLVM, PowerPC.
Herald added subscribers: llvm-commits, shchenz, hiraditya.

This patch adds the td definitions and asm/disasm tests for the following instructions:

  VINSBVLX
  VINSBVRX
  VINSHVLX
  VINSHVRX
  VINSWVLX
  VINSWVRX
  VINSBLX
  VINSBRX
  VINSHLX
  VINSHRX
  VINSWLX
  VINSWRX
  VINSDLX
  VINSDRX
  
  VINSW
  VINSD


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D83052

Files:
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
  llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s

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