[PATCH] D82239: RISC-V machine attribute to disable floating-point division and square root instructions in codegen

[Bandhav Veluri via Phabricator via llvm-commits]

vb000 created this revision.
vb000 added a reviewer: asb.
vb000 added a project: LLVM.
Herald added subscribers: llvm-commits, luismarques, apazos, sameer.abuasal, pzheng, s.egerton, lenary, Jim, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya.

This patch implemented the subtarget feature `no-fdiv` to disable `fdiv.[s/d]` and `fsqrt.[s/d]` instructions when `F` or `D` extension is enabled:

- This implements the functionality same as `-mno-fdiv` provided by GCC's RISC-V backend (https://gcc.gnu.org/onlinedocs/gcc/RISC-V-Options.html).
- Errors when user enables this machine attribute but `F` or `D` extension is not enabled.
- Implementation is done during ISel Lowering using `setOperationAction` method on `ISD::FDIV` and `ISD::FSQRT` IR instructions.


Repository:
  rL LLVM

https://reviews.llvm.org/D82239

Files:
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/no-fdiv-attr.ll

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