[PATCH] D81979: [AArch64][GlobalISel] Port buildvector -> dup pattern from AArch64ISelLowering

[Jessica Paquette via Phabricator via llvm-commits]

paquette added a comment.

In D81979#2097404 <https://reviews.llvm.org/D81979#2097404>, @aemerson wrote:

> What's the reason for avoiding matching a constant lane build_vector?


I think that it's probably this comment in arm64-dup.ll:

  ; We used to spot this as a BUILD_VECTOR implementable by dup, but assume that
  ; the single value needed was of the same type as the vector. This is false if
  ; the scalar corresponding to the vector type is illegal (e.g. a <4 x i16>
  ; BUILD_VECTOR will have an i32 as its source). In that case, the operation is
  ; not a simple "dup vD.4h, vN.h[idx]" after all, and we crashed.
  ;
  ; *However*, it is a dup vD.4h, vN.h[2*idx].

This is wrt the following IR:

  define <4 x i16> @test_build_illegal(<4 x i32> %in) {
    %val = extractelement <4 x i32> %in, i32 3
    %smallval = trunc i32 %val to i16
    %vec = insertelement <4x i16> undef, i16 %smallval, i32 3
    ret <4 x i16> %vec
  }


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https://reviews.llvm.org/D81979