[PATCH] D81979: [AArch64][GlobalISel] Port buildvector -> dup pattern from AArch64ISelLowering

[Amara Emerson via Phabricator via llvm-commits]

aemerson added a comment.

What's the reason for avoiding matching a constant lane build_vector?



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Comment at: llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp:290
+  // %splat:fpr(<2 x s64>) = G_SHUFFLE_VECTOR %ins(<2 x s64>), %undef,
+  // %zerovec(<2 x s32>)
   //
----------------
misleading whitespace change.


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  https://reviews.llvm.org/D81979/new/

https://reviews.llvm.org/D81979