[PATCH] D81661: [VectorCombine] scalarize compares with insertelement operand(s)

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added inline comments.


================
Comment at: llvm/lib/Transforms/Vectorize/VectorCombine.cpp:324-325
 
+  // Do not convert the vector condition of a vector select into a scalar
+  // condition. That is likely to cause problems for codegen.
+  bool IsCmp = Pred != CmpInst::Predicate::BAD_ICMP_PREDICATE;
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This needs more words i'd say.

https://godbolt.org/z/4tqgwP
I believe the problem we are preventing is the differences in bit patterns for true/false between scalar and vector comparisons.
* https://www.felixcloutier.com/x86/setcc `Sets the destination operand to 0 or 1 depending on the settings of the status flags`
* https://www.felixcloutier.com/x86/pcmpeqb:pcmpeqw:pcmpeqd `If a pair of data elements is equal, the corresponding data element in the destination operand is set to all 1s`
* https://www.felixcloutier.com/x86/blendvps `depending on mask bits defined in the mask register operand. The mask bits are the most significant bit in each dword element of the mask register.`

And there are other variants on other targets. (there's enum, can't find it right now)

Can we just model that new extra cost?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81661/new/

https://reviews.llvm.org/D81661