[PATCH] D81661: [VectorCombine] scalarize compares with insertelement operand(s)

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: lebedev.ri, RKSimon, craig.topper, efriedma.
Herald added subscribers: hiraditya, mcrosier.
Herald added a project: LLVM.

Generalize scalarization (recently enhanced with D80885 <https://reviews.llvm.org/D80885>) to allow compares as well as binops.
Similar to binops, we are avoiding scalarization of a loaded value because that could avoid a register transfer in codegen.
This requires 1 extra predicate that I am aware of: we do not want to scalarize the condition value of a vector select. That might also invert a transform that we do in instcombine that prefers a vector condition operand for a vector select.

I think this is the final step in solving PR37463:
https://bugs.llvm.org/show_bug.cgi?id=37463


https://reviews.llvm.org/D81661

Files:
  llvm/lib/Transforms/Vectorize/VectorCombine.cpp
  llvm/test/Transforms/VectorCombine/X86/scalarize-cmp.ll

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