[PATCH] D80867: [x86] form reduction intrinsics over raw IR

[Sanjay Patel via Phabricator via llvm-commits]

spatel marked an inline comment as done.
spatel added inline comments.


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Comment at: llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-expanded.ll:258
 ; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[BIN_RDX4]], i32 0
-; CHECK-NEXT:    [[OP_EXTRA:%.*]] = fadd fast float [[TMP2]], 4.200000e+01
+; CHECK-NEXT:    [[BIN_RDX5:%.*]] = fadd fast float 0.000000e+00, [[TMP2]]
+; CHECK-NEXT:    [[OP_EXTRA:%.*]] = fadd fast float [[BIN_RDX5]], 4.200000e+01
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nick wrote:
> Is this expected behavior?
Yes, the "fadd fast 0.0" is expected as commented on previously in the review.
That's because the expansion pass is not doing any simplifications itself. We do expect SDAG or other codegen to simplify that. 

If that's not working as expected, please let me know.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80867/new/

https://reviews.llvm.org/D80867