[PATCH] D80867: [x86] form reduction intrinsics over raw IR

[Nikita Kniazev via Phabricator via llvm-commits]

nick added inline comments.


================
Comment at: llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-expanded.ll:258
 ; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[BIN_RDX4]], i32 0
-; CHECK-NEXT:    [[OP_EXTRA:%.*]] = fadd fast float [[TMP2]], 4.200000e+01
+; CHECK-NEXT:    [[BIN_RDX5:%.*]] = fadd fast float 0.000000e+00, [[TMP2]]
+; CHECK-NEXT:    [[OP_EXTRA:%.*]] = fadd fast float [[BIN_RDX5]], 4.200000e+01
----------------
Is this expected behavior?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80867/new/

https://reviews.llvm.org/D80867