[PATCH] D81587: [GlobalISel] Add missing properties to G_BRINDIRECT, G_BRJT

[Dominik Montada via Phabricator via llvm-commits]

gargaroff created this revision.
gargaroff added reviewers: aemerson, qcolombet, dsanders.
Herald added subscribers: llvm-commits, rovka.
Herald added a project: LLVM.
gargaroff added a comment.

I noticed the missing properties when implementing `analyzeBranch` for our downstream target. Since the machine verifier also uses this function, all of the GMIR was passing through it and we were getting false-positives for those two instructions. Seems like an obvious fix. I guess the two tests changed because now there is no implicit fall-through, which marks the basic block as a successor.


Add `isBarrier`, `isIndirectBranch` to `G_BRINDIRECT` and `G_BRJT`.
Without these, `MachineInstr.isConditionalBranch()` was giving a
false-positive for those instructions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D81587

Files:
  llvm/include/llvm/Target/GenericOpcodes.td
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir


Index: llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir
@@ -30,7 +30,6 @@
 body:             |
   ; CHECK-LABEL: name: test_blockaddress
   ; CHECK: bb.0 (%ir-block.0):
-  ; CHECK:   successors: %bb.1(0x80000000)
   ; CHECK:   [[MOVaddrBA:%[0-9]+]]:gpr64 = MOVaddrBA target-flags(aarch64-page) blockaddress(@test_blockaddress, %ir-block.block), target-flags(aarch64-pageoff, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block)
   ; CHECK:   [[MOVaddr:%[0-9]+]]:gpr64common = MOVaddr target-flags(aarch64-page) @addr, target-flags(aarch64-pageoff, aarch64-nc) @addr
   ; CHECK:   STRXui [[MOVaddrBA]], [[MOVaddr]], 0 :: (store 8 into @addr)
@@ -39,7 +38,6 @@
   ; CHECK:   RET_ReallyLR
   ; LARGE-LABEL: name: test_blockaddress
   ; LARGE: bb.0 (%ir-block.0):
-  ; LARGE:   successors: %bb.1(0x80000000)
   ; LARGE:   [[MOVZXi:%[0-9]+]]:gpr64 = MOVZXi target-flags(aarch64-g0, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block), 0
   ; LARGE:   [[MOVKXi:%[0-9]+]]:gpr64 = MOVKXi [[MOVZXi]], target-flags(aarch64-g1, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block), 16
   ; LARGE:   [[MOVKXi1:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi]], target-flags(aarch64-g2, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block), 32
Index: llvm/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir
@@ -25,7 +25,6 @@
 body:             |
   ; CHECK-LABEL: name: test_blockaddress
   ; CHECK: bb.0 (%ir-block.0):
-  ; CHECK:   successors: %bb.1(0x80000000)
   ; CHECK:   [[BLOCK_ADDR:%[0-9]+]]:_(p0) = G_BLOCK_ADDR blockaddress(@test_blockaddress, %ir-block.block)
   ; CHECK:   [[ADRP:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @addr
   ; CHECK:   [[ADD_LOW:%[0-9]+]]:_(p0) = G_ADD_LOW [[ADRP]](p0), target-flags(aarch64-pageoff, aarch64-nc) @addr
Index: llvm/include/llvm/Target/GenericOpcodes.td
===================================================================
--- llvm/include/llvm/Target/GenericOpcodes.td
+++ llvm/include/llvm/Target/GenericOpcodes.td
@@ -1085,6 +1085,8 @@
   let hasSideEffects = 0;
   let isBranch = 1;
   let isTerminator = 1;
+  let isBarrier = 1;
+  let isIndirectBranch = 1;
 }
 
 // Generic branch to jump table entry
@@ -1094,6 +1096,8 @@
   let hasSideEffects = 0;
   let isBranch = 1;
   let isTerminator = 1;
+  let isBarrier = 1;
+  let isIndirectBranch = 1;
 }
 
 def G_READ_REGISTER : GenericInstruction {


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