[PATCH] D79598: [AArch64][SVE] Add patterns for VSELECT of immediates.

[Eli Friedman via Phabricator via llvm-commits]

efriedma marked an inline comment as done.
efriedma added a comment.

Say you have something like `x < 0 ? 0 : 1`.  That doesn't match.  But if you rewrite it to `x >= 0 ? 1 : 0`, it does.



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Comment at: llvm/test/CodeGen/AArch64/sve-vselect-imm.ll:114
+
+; TODO: We could actually use something like "sel z0.b, p0/z, #-128" if the
+; odd bits of the predicate are zero.
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fpetrogalli wrote:
> I am probably missing something trivial, but why would this be the case only if the odd bits if the predicate are zero?
> 
> Moreover, why not add the patterns needed for this directly in this patch? IIUC a higher `AddedComplexity` is what you need to prioritize the current pattern over the `sel` one.
Using ACLE intrinsics, the suggestion is essentially doing something like `svreinterpret_s16(svsel(pred, svdup_s8(-128), svdup_s8(0)))`.  Note that this is using the predicate as a `<vscale x 16 x i1>`, not a `<vscale x 8 x i1>`.

The pattern required for that is probably non-trivial


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