[PATCH] D76051: [WIP][RISCV][GlobalISel] Select register banks for GPR ALU instructions

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill updated this revision to Diff 255752.
lewis-revill added a comment.

Support AND/OR/XOR.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76051/new/

https://reviews.llvm.org/D76051

Files:
  llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterBankInfo.h
  llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu32.mir
  llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu64.mir

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