[PATCH] D42616: [X86] Emit 11-byte or 15-byte NOPs on recent AMD targets, else default to 10-byte NOPs (PR22965)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

In D42616#1913426 <https://reviews.llvm.org/D42616#1913426>, @reames wrote:

> Looking at this commit, I can't find any information about which platform triggered the switch from 15 byte to 10 byte nops by default.  From what I can tell reading through Agner's guides, it really looks like modern Intel's should also handle the 15 byte form (as they can decode an unlimited number of prefixes w/o stalls).  Was this simply missed in the review discussion, or is there some bit of context here I'm missing?


IIRC the info for recent Intel targets wasn't available apart from a little info in Agner's docs and I think the Intel AOM recommended 10bytes. I'm not sure where the SLM limit came from and why its not all Atom arch but I seem to have kept it to 7bytes.

AMD's per-family SoGs usually recommend a upper limit so we used that info for each specific AMD cpu family.

As ever patches welcome for specific CPUs :-)


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