[PATCH] D42616: [X86] Emit 11-byte or 15-byte NOPs on recent AMD targets, else default to 10-byte NOPs (PR22965)

[Philip Reames via Phabricator via llvm-commits]

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Replying to a very old review thread...

Looking at this commit, I can't find any information about which platform triggered the switch from 15 byte to 10 byte nops by default.  From what I can tell reading through Agner's guides, it really looks like modern Intel's should also handle the 15 byte form (as they can decode an unlimited number of prefixes w/o stalls).  Was this simply missed in the review discussion, or is there some bit of context here I'm missing?

p.s. In the original discussion, padding instructions for alignment was mentioned as an alternative.  Amusingly enough, that's what I'm now working on which triggered this question.  (see D75203 <https://reviews.llvm.org/D75203> and D75300 <https://reviews.llvm.org/D75300>)


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