[PATCH] D75699: [mlir] [VectorOps] Merge VectorReduction/VectorReductionV2 into one Op

[River Riddle via Phabricator via llvm-commits]

rriddle added inline comments.


================
Comment at: mlir/lib/Dialect/VectorOps/VectorOps.cpp:98
+
+static ParseResult parseReductionOp(OpAsmParser &parser,
+                                    OperationState &result) {
----------------
nicolasvasilache wrote:
> Re assembly format, file a bug for @rriddle linking to this diff?
> Another way, if variadic is more tricky to impl automatically (because of say combinatorial effects with variadic operands), could be to allow multiple declarative forms and a simple convention on optional arg ordering?
It already does: https://mlir.llvm.org/docs/OpDefinitions/#optional-groups


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75699/new/

https://reviews.llvm.org/D75699