[PATCH] D75371: [ARM] Optimise ASRL/LSRL to smaller shifts using demand bits.

[Dave Green via Phabricator via llvm-commits]

This revision was not accepted when it landed; it landed in state "Needs Review".
This revision was automatically updated to reflect the committed changes.
Closed by commit rG38e532278e31: [LSR] Add masked load and store handling (authored by dmgreen).

Changed prior to commit:
  https://reviews.llvm.org/D75371?vs=247305&id=248243#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75371/new/

https://reviews.llvm.org/D75371

Files:
  llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
  llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D75371.248243.patch
Type: text/x-patch
Size: 23233 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200304/9fd45d35/attachment.bin>