[PATCH] D75580: [llvm][CodeGen][SVE] Implement IR intrinsics for gather prefetch.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


================
Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:1280
+                ],
+                [IntrInaccessibleMemOrArgMemOnly, ImmArg<1>, ImmArg<3>]>;
+
----------------
Because the ACLE intrinsic doesn't require the offset to be an immediate, we don't want ImmArg<1> to be an immediate in the LLVM IR intrinsic, and rather leave it to CodeGen to make sure it generates the appropriate instruction.


================
Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:40
+   : gather_prf_scaled_pat_frag<int_aarch64_sve_gather_prf_scaled_uxtw,
+   [{ return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::nxv4i16 || cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::nxv4f16; }]>;
+
----------------
nit: format to split statement on two lines?


================
Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:6449
   def _SXTW_SCALED : sve_mem_32b_prfm_sv<msz, 1, asm, sxtw_opnd>;
+     def : Pat<(op_uxtw (i64 GPR64sp:$Rn), (nxv4i32 uxtw_opnd:$Zm), (nxv4i1 PPR3bAny:$Pg), (i32 sve_prfop:$prfop)),
+          (!cast<Instruction>(NAME # _UXTW_SCALED) sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm)>;
----------------
nit: this is some odd formatting here.


================
Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-gather-prefetches-scaled-offset.ll:4
+; PRFB <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod>]    -> 32-bit          scaled offset
+declare void @llvm.aarch64.sve.gather.prf.scaled.uxtw.p0i8.nx4vi32(i8* %base, <vscale x 4 x i32> %offset, <vscale x 4 x i1> %Pg, i32 %prfop)
+
----------------
nit: Most tests have the declarations at the bottom.
nit: There are some random newlines in this file.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75580/new/

https://reviews.llvm.org/D75580