[PATCH] D75086: [AArch64][GlobalISel] Fixup <32b heterogeneous regbanks of G_PHIs just before selection.

[Amara Emerson via Phabricator via llvm-commits]

aemerson added a comment.

In D75086#1894223 <https://reviews.llvm.org/D75086#1894223>, @qcolombet wrote:

> > s16 operations, if legal, just get selected to gpr32 regclass instructions. E.g.
>
>   %ld:gpr(s16) = G_LOAD ...
>   =>
>   %ld:gpr32 = LDR_16 ...
>
>
> That's interesting, because that means you have inreg extension where you would have regular extension in the IR.
>  E.g.,
>
>   s16 = G_LOAD
>   s32 = G_ZEXT s16
>
>
> =>
>
>   gpr32 = LDR_16
>   gpr32 = G_ZEXT gpr32
>
>
> I would have expected that instead we would have combined loads with the related extension to from an extended load.


Yes, on AArch64 all sub-32bit loads give a free ZEXT. We catch this case in the selector if for some reason we have a redundant ZEXT.

> Anyway, I guess this ship has sailed.
> 
> LGTM.




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