[PATCH] D74254: [llvm][aarch64] SVE addressing modes.

[Francesco Petrogalli via Phabricator via llvm-commits]

fpetrogalli marked 3 inline comments as done.
fpetrogalli added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:4473
+  const SDValue ShiftRHS = RHS.getOperand(1);
+  auto *C = dyn_cast<ConstantSDNode>(ShiftRHS);
+  if (nullptr == C)
----------------
sdesmalen wrote:
> ```if (auto *C = dyn_cast<ConstantSDNode>(ShiftRHS)) {
>   if (ShiftAmount == C->getZExtValue()) {
>     ...
>     return true;
>   }
> }
> 
> return false;```
@sdesmalen, your version saves some lines, I'll apply it and then submit the patch. Thank you!


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Comment at: llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll:250
+                                      <vscale x 2 x i8> *%base_load,
+                                      i32 8,
+                                      <vscale x 2 x i1> %mask)
----------------
sdesmalen wrote:
> nit: did you chose a different alignment here on purpose?
No  - it is not on purpose. Do you want me to set everything to 1?  I wouldn't bother, non of the code added in this patch care of the value of the alignment...


Repository:
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  https://reviews.llvm.org/D74254/new/

https://reviews.llvm.org/D74254