[llvm] 97f1160 - [X86] Don't bother avoiding illegal FCMOVs if we don't have the cmov subtarget feature.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 21 00:35:20 PST 2020
Author: Craig Topper
Date: 2020-02-21T00:34:15-08:00
New Revision: 97f11600e0b87b69b01412af8df4fc37af652fce
URL: https://github.com/llvm/llvm-project/commit/97f11600e0b87b69b01412af8df4fc37af652fce
DIFF: https://github.com/llvm/llvm-project/commit/97f11600e0b87b69b01412af8df4fc37af652fce.diff
LOG: [X86] Don't bother avoiding illegal FCMOVs if we don't have the cmov subtarget feature.
We'll be forced to emit branches so we might as well use the most
direct condition.
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/cmov-fp.ll
llvm/test/CodeGen/X86/pseudo_cmov_lower.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 8fd4e4d85c57..7f6d36de7150 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -22583,7 +22583,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
SDValue Cmp = Cond.getOperand(1);
bool IllegalFPCMov = false;
if (VT.isFloatingPoint() && !VT.isVector() &&
- !isScalarFPTypeInSSEReg(VT)) // FPStack?
+ !isScalarFPTypeInSSEReg(VT) && Subtarget.hasCMov()) // FPStack?
IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
@@ -39253,7 +39253,7 @@ static SDValue combineCMov(SDNode *N, SelectionDAG &DAG,
if (!(FalseOp.getValueType() == MVT::f80 ||
(FalseOp.getValueType() == MVT::f64 && !Subtarget.hasSSE2()) ||
(FalseOp.getValueType() == MVT::f32 && !Subtarget.hasSSE1())) ||
- hasFPCMov(CC)) {
+ !Subtarget.hasCMov() || hasFPCMov(CC)) {
SDValue Ops[] = {FalseOp, TrueOp, DAG.getTargetConstant(CC, DL, MVT::i8),
Flags};
return DAG.getNode(X86ISD::CMOV, DL, N->getValueType(0), Ops);
diff --git a/llvm/test/CodeGen/X86/cmov-fp.ll b/llvm/test/CodeGen/X86/cmov-fp.ll
index 4d02666f187a..756324bbdfdc 100644
--- a/llvm/test/CodeGen/X86/cmov-fp.ll
+++ b/llvm/test/CodeGen/X86/cmov-fp.ll
@@ -310,10 +310,8 @@ define double @test5(i32 %a, i32 %b, double %x) nounwind {
; NOCMOV-NEXT: fldl {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: setg %al
-; NOCMOV-NEXT: testb %al, %al
; NOCMOV-NEXT: flds {{\.LCPI.*}}
-; NOCMOV-NEXT: jne .LBB4_2
+; NOCMOV-NEXT: jg .LBB4_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz
@@ -379,10 +377,8 @@ define double @test6(i32 %a, i32 %b, double %x) nounwind {
; NOCMOV-NEXT: fldl {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: setge %al
-; NOCMOV-NEXT: testb %al, %al
; NOCMOV-NEXT: flds {{\.LCPI.*}}
-; NOCMOV-NEXT: jne .LBB5_2
+; NOCMOV-NEXT: jge .LBB5_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz
@@ -448,10 +444,8 @@ define double @test7(i32 %a, i32 %b, double %x) nounwind {
; NOCMOV-NEXT: fldl {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: setl %al
-; NOCMOV-NEXT: testb %al, %al
; NOCMOV-NEXT: flds {{\.LCPI.*}}
-; NOCMOV-NEXT: jne .LBB6_2
+; NOCMOV-NEXT: jl .LBB6_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz
@@ -517,10 +511,8 @@ define double @test8(i32 %a, i32 %b, double %x) nounwind {
; NOCMOV-NEXT: fldl {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: setle %al
-; NOCMOV-NEXT: testb %al, %al
; NOCMOV-NEXT: flds {{\.LCPI.*}}
-; NOCMOV-NEXT: jne .LBB7_2
+; NOCMOV-NEXT: jle .LBB7_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz
@@ -846,10 +838,8 @@ define float @test13(i32 %a, i32 %b, float %x) nounwind {
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: setg %al
-; NOCMOV-NEXT: testb %al, %al
; NOCMOV-NEXT: flds {{\.LCPI.*}}
-; NOCMOV-NEXT: jne .LBB12_2
+; NOCMOV-NEXT: jg .LBB12_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz
@@ -915,10 +905,8 @@ define float @test14(i32 %a, i32 %b, float %x) nounwind {
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: setge %al
-; NOCMOV-NEXT: testb %al, %al
; NOCMOV-NEXT: flds {{\.LCPI.*}}
-; NOCMOV-NEXT: jne .LBB13_2
+; NOCMOV-NEXT: jge .LBB13_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz
@@ -984,10 +972,8 @@ define float @test15(i32 %a, i32 %b, float %x) nounwind {
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: setl %al
-; NOCMOV-NEXT: testb %al, %al
; NOCMOV-NEXT: flds {{\.LCPI.*}}
-; NOCMOV-NEXT: jne .LBB14_2
+; NOCMOV-NEXT: jl .LBB14_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz
@@ -1053,10 +1039,8 @@ define float @test16(i32 %a, i32 %b, float %x) nounwind {
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: setle %al
-; NOCMOV-NEXT: testb %al, %al
; NOCMOV-NEXT: flds {{\.LCPI.*}}
-; NOCMOV-NEXT: jne .LBB15_2
+; NOCMOV-NEXT: jle .LBB15_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz
@@ -1308,7 +1292,6 @@ define x86_fp80 @test21(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOSSE2-NEXT: fstp %st(1)
; NOSSE2-NEXT: retl
;
-; We don't emit a branch for fp80, why?
; NOSSE1-LABEL: test21:
; NOSSE1: # %bb.0:
; NOSSE1-NEXT: fldt {{[0-9]+}}(%esp)
@@ -1327,10 +1310,8 @@ define x86_fp80 @test21(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOCMOV-NEXT: fldt {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: setg %al
-; NOCMOV-NEXT: testb %al, %al
; NOCMOV-NEXT: flds {{\.LCPI.*}}
-; NOCMOV-NEXT: jne .LBB20_2
+; NOCMOV-NEXT: jg .LBB20_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz
@@ -1338,6 +1319,7 @@ define x86_fp80 @test21(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOCMOV-NEXT: .LBB20_2:
; NOCMOV-NEXT: fstp %st(1)
; NOCMOV-NEXT: retl
+; We don't emit a branch for fp80, why?
%cmp = icmp sgt i32 %a, %b
%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
ret x86_fp80 %sel
@@ -1388,10 +1370,8 @@ define x86_fp80 @test22(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOCMOV-NEXT: fldt {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: setge %al
-; NOCMOV-NEXT: testb %al, %al
; NOCMOV-NEXT: flds {{\.LCPI.*}}
-; NOCMOV-NEXT: jne .LBB21_2
+; NOCMOV-NEXT: jge .LBB21_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz
@@ -1449,10 +1429,8 @@ define x86_fp80 @test23(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOCMOV-NEXT: fldt {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: setl %al
-; NOCMOV-NEXT: testb %al, %al
; NOCMOV-NEXT: flds {{\.LCPI.*}}
-; NOCMOV-NEXT: jne .LBB22_2
+; NOCMOV-NEXT: jl .LBB22_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz
@@ -1510,10 +1488,8 @@ define x86_fp80 @test24(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; NOCMOV-NEXT: fldt {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
-; NOCMOV-NEXT: setle %al
-; NOCMOV-NEXT: testb %al, %al
; NOCMOV-NEXT: flds {{\.LCPI.*}}
-; NOCMOV-NEXT: jne .LBB23_2
+; NOCMOV-NEXT: jle .LBB23_2
; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz
diff --git a/llvm/test/CodeGen/X86/pseudo_cmov_lower.ll b/llvm/test/CodeGen/X86/pseudo_cmov_lower.ll
index 3e36c830ee27..c59e3478ff51 100644
--- a/llvm/test/CodeGen/X86/pseudo_cmov_lower.ll
+++ b/llvm/test/CodeGen/X86/pseudo_cmov_lower.ll
@@ -66,8 +66,8 @@ entry:
; This test checks that only a single js gets generated in the final code
; for lowering the CMOV pseudos that get created for this IR.
; CHECK-LABEL: foo4:
-; CHECK: jne
-; CHECK-NOT: jne
+; CHECK: js
+; CHECK-NOT: js
define float @foo4(i32 %v1, float %v2, float %v3, float %v4) nounwind {
entry:
%cmp = icmp slt i32 %v1, 0
More information about the llvm-commits
mailing list