[PATCH] D74856: [AArch64][SVE] Add backend support for splats of immediates

Cameron McInally via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Feb 19 15:15:11 PST 2020


cameron.mcinally marked 4 inline comments as done.
cameron.mcinally added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:13
 
+def SVE8BitLslImm : ComplexPattern<i32, 2, "SelectSVE8BitLslImm", [imm]>;
+
----------------
efriedma wrote:
> Is there some reason you can't use the existing cpy_imm8_opt_lsl_i8?
I'm not sure I understand this one. What should I replace with cpy_imm8_opt_lsl_i8?

SVE8BitLslImm is looking for two i8 immediates (i8 value and i8 shift amount).

cpy_imm8_opt_lsl_i8 is just checking for one i8 immediate, IINM.


================
Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:342
+    def : Pat<(nxv2f64 (AArch64dup fpimm64:$imm8)),
+              (FDUP_ZI_D fpimm64:$imm8)>;
+  }
----------------
efriedma wrote:
> This is a little inconsistent with the other patterns: I think we also need need nxv2f32/nxv4f16/nxv2f16?
Good catch. The f16 tests don't really work, so didn't catch the missing patterns. The nxv2f32 pattern was there.

Added the missing patterns.


================
Comment at: llvm/test/CodeGen/AArch64/sve-vector-splat.ll:306
+; CHECK-LABEL: splat_nxv4f32_imm:
+; CHECK: mov z0.s, #1
+; CHECK-NEXT: ret
----------------
efriedma wrote:
> It looks like splat_nxv4f32_imm is returning the integer 1, not the floating-point 1.0?
Just a bad copy-and-paste. Updated.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D74856/new/

https://reviews.llvm.org/D74856





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