[PATCH] D74822: [AArch64][ASMParser] Refuse equal source/destination for LDRAA/LDRAB

[Pierre van Houtryve via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG39cecabece8c: [AArch64][ASMParser] Refuse equal source/destination for LDRAA/LDRAB (authored by Pierre-vh).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D74822/new/

https://reviews.llvm.org/D74822

Files:
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/test/MC/AArch64/armv8.3a-diagnostics.s
  llvm/test/MC/AArch64/armv8.3a-signed-pointer.s


Index: llvm/test/MC/AArch64/armv8.3a-signed-pointer.s
===================================================================
--- llvm/test/MC/AArch64/armv8.3a-signed-pointer.s
+++ llvm/test/MC/AArch64/armv8.3a-signed-pointer.s
@@ -327,3 +327,11 @@
 // CHECK-NEXT: ldrab x0, [x1, #0]!  // encoding: [0x20,0x0c,0xa0,0xf8]
 // CHECK-REQ: error: instruction requires: pa
 // CHECK-REQ-NEXT:  ldrab x0, [x1]!
+  ldraa xzr, [sp, -4096]!
+// CHECK-NEXT: ldraa xzr, [sp, #-4096]!  // encoding: [0xff,0x0f,0x60,0xf8]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  ldraa xzr, [sp, -4096]!
+  ldrab xzr, [sp, -4096]!
+// CHECK-NEXT: ldrab xzr, [sp, #-4096]!  // encoding: [0xff,0x0f,0xe0,0xf8]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  ldrab xzr, [sp, -4096]!
Index: llvm/test/MC/AArch64/armv8.3a-diagnostics.s
===================================================================
--- llvm/test/MC/AArch64/armv8.3a-diagnostics.s
+++ llvm/test/MC/AArch64/armv8.3a-diagnostics.s
@@ -18,3 +18,15 @@
 // CHECK: error: index must be a multiple of 8 in range [-4096, 4088].
   ldrab x0, [x1, 4086]
 // CHECK: error: index must be a multiple of 8 in range [-4096, 4088].
+  ldraa x0, [x0, -4096]!
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable LDRA instruction, writeback base is also a destination
+  ldrab x0, [x0, -4096]!
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable LDRA instruction, writeback base is also a destination
+  ldraa xzr, [xzr, -4096]!
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+  ldraa sp, [sp, -4096]!
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+  ldrab xzr, [xzr, -4096]!
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+  ldrab sp, [sp, -4096]!
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
Index: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
===================================================================
--- llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -4114,6 +4114,16 @@
                    "unpredictable STXP instruction, status is also a source");
     break;
   }
+  case AArch64::LDRABwriteback:
+  case AArch64::LDRAAwriteback: {
+    unsigned Xt = Inst.getOperand(0).getReg();
+    unsigned Xn = Inst.getOperand(1).getReg();
+    if (Xt == Xn)
+      return Error(Loc[0],
+          "unpredictable LDRA instruction, writeback base"
+          " is also a destination");
+    break;
+  }
   }
 
 


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