[PATCH] D74471: [AArch64][SVE] Add predicate reinterpret intrinsics

[Sander de Smalen via Phabricator via llvm-commits]

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In D74471#1881394 <https://reviews.llvm.org/D74471#1881394>, @efriedma wrote:

> Do you mean the way the C intrinsics are lowered gives some protection?


Correct, the intrinsics are intended to be created by the Clang ACLE implementation, which will reinterpret-cast the predicate results to svbool_t. Without optimisations that introduce a pattern like you describe, nothing breaks in practice. Of course when we will start adding such optimisations, that changes things.

I'm happy with the decision to focus on correctness first though, it probably shouldn't be too hard to fold away the explicit zeroing.

@c-rhodes can you update this patch to explicitly zero the other lanes?


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