[PATCH] D73179: [IR] masked gather/scatter alignment should be set

[Guillaume Chatelet via Phabricator via llvm-commits]

gchatelet marked 2 inline comments as done.
gchatelet added inline comments.


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Comment at: llvm/test/CodeGen/X86/avx2-masked-gather.ll:54
   %ld  = load <2 x i32*>, <2 x i32*>* %ptr
-  %res = call <2 x i32> @llvm.masked.gather.v2i32(<2 x i32*> %ld, i32 0, <2 x i1> %masks, <2 x i32> %passthro)
+  %res = call <2 x i32> @llvm.masked.gather.v2i32(<2 x i32*> %ld, i32 1, <2 x i1> %masks, <2 x i32> %passthro)
   ret <2 x i32> %res
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delena wrote:
> I think 0 is also good. You can put alignment 0 in load/store.
It seems like it's not the case for **masked** load / store
[unittest](https://github.com/llvm/llvm-project/blob/master/llvm/test/Verifier/masked-load.ll)
[godbolt](https://godbolt.org/z/hdaTpm)

Alignment needs to be a non 0 power of two.

Any reasons why we would want it to be 0?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D73179/new/

https://reviews.llvm.org/D73179