[PATCH] D72709: [codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU.

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


================
Comment at: llvm/test/CodeGen/AMDGPU/dead-mi-use-same-intr.mir:17
   %1 = IMPLICIT_DEF
-  dead %2:vgpr_32 = V_MAC_F32_e32 %0:vgpr_32, %1:vgpr_32, undef %2:vgpr_32, implicit $exec
+  dead %3:vgpr_32 = V_MAC_F32_e32 %0:vgpr_32, %1:vgpr_32, undef %2:vgpr_32, implicit $exec
   S_ENDPGM 0
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hliao wrote:
> rampitec wrote:
> > The test became useless. The point was to check def of the same reg as use in the same instruction past SSA.
> `dead-mi-elimination` only works for SSA form. If we really need a DIE for non-SSA MIR, we need to check dead def with live range.
Still the test became useless and needs to be removed with this change.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72709/new/

https://reviews.llvm.org/D72709