[PATCH] D72709: [codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU.

[Michael Liao via Phabricator via llvm-commits]

hliao added a comment.

In D72709#1820182 <https://reviews.llvm.org/D72709#1820182>, @rampitec wrote:

> You have skipped the dead MO, but was pass reordering really necessary? It seems we have higher register pressure with this change.


The issue is that DIE on MIR assumes SSA form MIR. It's incorrect to run it after DeSSA. It results in invalid IR. I thought we should fix this first and look into the fix for the higher register pressure issue here.


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https://reviews.llvm.org/D72709