[PATCH] D72392: [MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

The diff in `llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll` is:

          adrp    x8, .LCPI0_0
  -       ldr     h0, [x8, :lo12:.LCPI0_0]
          movi    v1.2d, #0000000000000000
          movi    v2.2d, #0000000000000000
  +       ldr     h0, [x8, :lo12:.LCPI0_0]
          movi    v3.2d, #0000000000000000

The scheduler prefers not to put the ldr immediately after the adrp because of the register dependency on x8 with latency 1.


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https://reviews.llvm.org/D72392