[PATCH] D66210: [RISCV] Enable the machine outliner for RISC-V

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill added a comment.

So the failure in the GCC testsuite occurs due to the following test:

  /* PR rtl-optimization/48141 */
  /* { dg-do compile } */
  /* { dg-options "-O" } */
  
  #define A i = 0;
  #define B A A A A A A A A A A
  #define C B B B B B B B B B B
  #define D C C C C C C C C C C
  #define E D D D D D D D D D D
  
  int
  foo (void)
  {
    volatile int i = 0;
    E E E E E E E E E E E
    return 0;
  }

Which generates a huge amount of work for the machine outliner algorithm to process. I get a segmentation fault when the machine outliner attempts to iterate over the tree to add suffix indices.

Obviously it would be nice for the compiler not to segfault and I'll carry on looking into this further. However I don't see that this indicates a problem with the RISC-V backend specific logic added by this patch, so if there's no objection I may go ahead with merging this later.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D66210/new/

https://reviews.llvm.org/D66210