[llvm] 2675a3c - [AArch64] Be more careful to skip debug operands in LdSt Optimizier.
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 11 10:47:57 PST 2019
Author: Florian Hahn
Date: 2019-12-11T18:47:45Z
New Revision: 2675a3c8806a0995f204efe999db6001f6e700cf
URL: https://github.com/llvm/llvm-project/commit/2675a3c8806a0995f204efe999db6001f6e700cf
DIFF: https://github.com/llvm/llvm-project/commit/2675a3c8806a0995f204efe999db6001f6e700cf.diff
LOG: [AArch64] Be more careful to skip debug operands in LdSt Optimizier.
This fixes crashes with $noreg operands.
Added:
Modified:
llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
llvm/test/CodeGen/AArch64/stp-opt-with-renaming-debug.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
index 2ffeea8db7b2..1bf882b66824 100644
--- a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -813,7 +813,7 @@ static bool forAllMIsUntilDef(MachineInstr &MI, MCPhysReg DefReg,
--Limit;
bool isDef = any_of(I->operands(), [DefReg, TRI](MachineOperand &MOP) {
- return MOP.isReg() && MOP.isDef() &&
+ return MOP.isReg() && MOP.isDef() && !MOP.isDebug() && MOP.getReg() &&
TRI->regsOverlap(MOP.getReg(), DefReg);
});
if (!Fn(*I, isDef))
@@ -880,7 +880,7 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
for (auto &MOP : MI.operands()) {
// Rename the first explicit definition and all implicit
// definitions matching RegToRename.
- if (MOP.isReg() &&
+ if (MOP.isReg() && !MOP.isDebug() && MOP.getReg() &&
(!SeenDef || (MOP.isDef() && MOP.isImplicit())) &&
TRI->regsOverlap(MOP.getReg(), RegToRename)) {
assert((MOP.isImplicit() ||
@@ -892,7 +892,8 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
}
} else {
for (auto &MOP : MI.operands()) {
- if (MOP.isReg() && TRI->regsOverlap(MOP.getReg(), RegToRename)) {
+ if (MOP.isReg() && !MOP.isDebug() && MOP.getReg() &&
+ TRI->regsOverlap(MOP.getReg(), RegToRename)) {
assert(MOP.isImplicit() ||
(MOP.isRenamable() && !MOP.isEarlyClobber()) &&
"Need renamable operands");
@@ -913,7 +914,7 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
std::next(I), std::next(Paired)))
assert(all_of(MI.operands(),
[this, &RenameReg](const MachineOperand &MOP) {
- return !MOP.isReg() || MOP.isDebug() ||
+ return !MOP.isReg() || MOP.isDebug() || !MOP.getReg() ||
!TRI->regsOverlap(MOP.getReg(), *RenameReg);
}) &&
"Rename register used between paired instruction, trashing the "
@@ -1348,7 +1349,8 @@ canRenameUpToDef(MachineInstr &FirstMI, LiveRegUnits &UsedInBetween,
if (!getLdStRegOp(FirstMI).isKill() &&
!any_of(FirstMI.operands(),
[TRI, RegToRename](const MachineOperand &MOP) {
- return MOP.isReg() && MOP.isImplicit() && MOP.isKill() &&
+ return MOP.isReg() && !MOP.isDebug() && MOP.getReg() &&
+ MOP.isImplicit() && MOP.isKill() &&
TRI->regsOverlap(RegToRename, MOP.getReg());
})) {
LLVM_DEBUG(dbgs() << " Operand not killed at " << FirstMI << "\n");
@@ -1384,7 +1386,7 @@ canRenameUpToDef(MachineInstr &FirstMI, LiveRegUnits &UsedInBetween,
// For defs, check if we can rename the first def of RegToRename.
if (FoundDef) {
for (auto &MOP : MI.operands()) {
- if (!MOP.isReg() || !MOP.isDef() ||
+ if (!MOP.isReg() || !MOP.isDef() || MOP.isDebug() || !MOP.getReg() ||
!TRI->regsOverlap(MOP.getReg(), RegToRename))
continue;
if (!canRenameMOP(MOP)) {
@@ -1397,7 +1399,8 @@ canRenameUpToDef(MachineInstr &FirstMI, LiveRegUnits &UsedInBetween,
return true;
} else {
for (auto &MOP : MI.operands()) {
- if (!MOP.isReg() || !TRI->regsOverlap(MOP.getReg(), RegToRename))
+ if (!MOP.isReg() || MOP.isDebug() || !MOP.getReg() ||
+ !TRI->regsOverlap(MOP.getReg(), RegToRename))
continue;
if (!canRenameMOP(MOP)) {
diff --git a/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-debug.mir b/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-debug.mir
index d6814549d1b0..8f573b67c524 100644
--- a/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-debug.mir
+++ b/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-debug.mir
@@ -1,6 +1,7 @@
# RUN: llc -run-pass=aarch64-ldst-opt -mtriple=arm64-apple-iphoneos -verify-machineinstrs -o - %s | FileCheck %s
--- |
- define void @test_dbg_value() #0 { ret void }
+ define void @test_dbg_value1() #0 { ret void }
+ define void @test_dbg_value2() #0 { ret void }
!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "llvm", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
!1 = !DIFile(filename: "dbg.ll", directory: "/tmp")
@@ -13,7 +14,7 @@
---
# Check we do not crash when checking $noreg debug operands.
#
-# CHECK-LABEL: name: test_dbg_value
+# CHECK-LABEL: name: test_dbg_value1
# CHECK: bb.0:
# CHECK-NEXT: liveins: $x0, $x1
# CHECK: $x10, renamable $x8 = LDPXi renamable $x0, 0 :: (load 8)
@@ -23,7 +24,7 @@
# CHECK-NEXT: renamable $x8 = ADDXrr $x8, $x8
# CHECK-NEXT: STPXi renamable $x8, killed $x10, renamable $x0, 10 :: (store 8, align 4)
# CHECK-NEXT: RET undef $lr
-name: test_dbg_value
+name: test_dbg_value1
alignment: 4
tracksRegLiveness: true
liveins:
@@ -47,3 +48,38 @@ body: |
RET undef $lr
...
+
+# CHECK-LABEL: name: test_dbg_value2
+# CHECK: bb.0:
+# CHECK-NEXT: liveins: $x19, $x20, $x0
+
+# CHECK: $x8 = ORRXrs $xzr, $x0, 0
+# CHECK-NEXT: renamable $x0 = nuw ADDXri $x0, 8, 0
+# CHECK-NEXT: DBG_VALUE $x0, $noreg,
+# CHECK-NEXT: STRXui killed renamable $x8, renamable $x19, 2 :: (store 8)
+# CHECK-NEXT: $x8 = ADDXrs renamable $x0, killed renamable $x20, 0
+# CHECK-NEXT: STPXi $xzr, renamable $x8, renamable $x19, 0 :: (store 8)
+# CHECK-NEXT: RET undef $lr, implicit $x0
+name: test_dbg_value2
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$x0' }
+ - { reg: '$x1' }
+frameInfo:
+ maxAlignment: 1
+ maxCallFrameSize: 0
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $x19, $x20, $x0
+
+ $x8 = ORRXrs $xzr, $x0, 0
+ renamable $x0 = nuw ADDXri $x0, 8, 0
+ DBG_VALUE $x0, $noreg, !7, !DIExpression(), debug-location !9
+ STRXui killed renamable $x8, renamable $x19, 2 :: (store 8)
+ $x8 = ADDXrs renamable $x0, killed renamable $x20, 0
+ STRXui $xzr, renamable $x19, 0 :: (store 8)
+ STRXui killed renamable $x8, killed renamable $x19, 1 :: (store 8)
+ RET undef $lr, implicit $x0
+...
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