[PATCH] D70966: [ARM] Teach the Arm cost model that a Shift can be folded into other instructions

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: t.p.northover, SjoerdMeijer, samparker, ostannard, efriedma, spatel, craig.topper, RKSimon.
Herald added subscribers: jsji, kbarton, aheejin, hiraditya, kristof.beyls, jgravelle-google, sbc100, nhaehnle, jvesely, nemanjai, dschuff, arsenm, jholewinski.
Herald added a project: LLVM.

This attempts to teach the cost model in Arm that code such as:

  %s = shl i32 %a, 3
  %a = and i32 %s, %b

Can under Arm or Thumb2 become:

  and r0, r1, r2, lsl #3

So the cost of the shift can essentially be free. To do this without trying to artificially adjust the cost of the "and" instruction, it needs to get the users of the shl and check if they are a type of instruction that the shift can be folded into. And so it needs to have access to the actual instruction in getArithmeticInstrCost, which if available is added as an extra parameter much like getCastInstrCost.

We otherwise limit it to shifts with a single user, which should hopefully handle most of the cases. The list of instruction that the shift can be folded into include ADC, ADD, AND, BIC, CMP, EOR, MVN, ORR, ORN, RSB, SBC and SUB. This translates to Add, Sub, And, Or, Xor and ICmp.


https://reviews.llvm.org/D70966

Files:
  llvm/include/llvm/Analysis/TargetTransformInfo.h
  llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
  llvm/include/llvm/CodeGen/BasicTTIImpl.h
  llvm/lib/Analysis/TargetTransformInfo.cpp
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
  llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
  llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
  llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
  llvm/lib/Target/ARM/ARMTargetTransformInfo.h
  llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
  llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
  llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h
  llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
  llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
  llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
  llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
  llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
  llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
  llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
  llvm/lib/Target/X86/X86TargetTransformInfo.cpp
  llvm/lib/Target/X86/X86TargetTransformInfo.h
  llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
  llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
  llvm/test/Transforms/LoopVectorize/ARM/mve-shiftcost.ll

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