[PATCH] D70795: [AArch64][SVE] Add intrinsics and patterns for logical predicate instructions

[Danilo Carvalho Grael via Phabricator via llvm-commits]

dancgr marked an inline comment as done.
dancgr added inline comments.


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Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:999
 
+def int_aarch64_sve_and_p       : AdvSIMD_Pred2VectorArg_Intrinsic;
+def int_aarch64_sve_bic_p       : AdvSIMD_Pred2VectorArg_Intrinsic;
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sdesmalen wrote:
> Is there a specific reason you're adding the `_p`? Most of the intrinsics that are predicated don't specify this, which kind of breaks with the convention with the other SVE intrinsics in this file. Note that we can represent an unpredicated `and` with existing selectiondag nodes so we wouldn't ever need an unpredicated `int_aarch64_sve_and`. It would be nice if you can change that for this and the other intrinsics before you commit the patch.
I added the _p because those are predicate to predicate operations, but we actually don't need the _p for the predicated predicate to predicate and predicated vector to vector instructions. The same intrinsic definition will work for both. I will be removing the _p before committing.


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  https://reviews.llvm.org/D70795/new/

https://reviews.llvm.org/D70795