[PATCH] D70795: [AArch64][SVE] Add intrinsics and patterns for logical predicate instructions

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


================
Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:999
 
+def int_aarch64_sve_and_p       : AdvSIMD_Pred2VectorArg_Intrinsic;
+def int_aarch64_sve_bic_p       : AdvSIMD_Pred2VectorArg_Intrinsic;
----------------
Is there a specific reason you're adding the `_p`? Most of the intrinsics that are predicated don't specify this, which kind of breaks with the convention with the other SVE intrinsics in this file. Note that we can represent an unpredicated `and` with existing selectiondag nodes so we wouldn't ever need an unpredicated `int_aarch64_sve_and`. It would be nice if you can change that for this and the other intrinsics before you commit the patch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70795/new/

https://reviews.llvm.org/D70795