[PATCH] D69326: [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine (3)

[Joan LLuch via Phabricator via llvm-commits]

joanlluch updated this revision to Diff 228156.
joanlluch edited the summary of this revision.
joanlluch added a comment.

Made sure diff matches latest trunk changes


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D69326/new/

https://reviews.llvm.org/D69326

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp


Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -3654,15 +3654,17 @@
           const APInt &AndRHSC = AndRHS->getAPIntValue();
           if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
             unsigned ShiftBits = AndRHSC.countTrailingZeros();
-            auto &DL = DAG.getDataLayout();
-            EVT ShiftTy = getShiftAmountTy(N0.getValueType(), DL,
-                                           !DCI.isBeforeLegalize());
-            EVT CmpTy = N0.getValueType();
-            SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
-                                        DAG.getConstant(ShiftBits, dl,
-                                                        ShiftTy));
-            SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, CmpTy);
-            return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
+            if (ShiftBits <= TLI.getShiftAmountThreshold(ShValTy)) {
+              auto &DL = DAG.getDataLayout();
+              EVT ShiftTy = getShiftAmountTy(ShValTy, DL,
+                                            !DCI.isBeforeLegalize());
+              EVT CmpTy = ShValTy;
+              SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
+                                          DAG.getConstant(ShiftBits, dl,
+                                                          ShiftTy));
+              SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, CmpTy);
+              return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
+            }
           }
         }
       } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
@@ -3684,11 +3686,12 @@
         }
         NewC.lshrInPlace(ShiftBits);
         if (ShiftBits && NewC.getMinSignedBits() <= 64 &&
-          isLegalICmpImmediate(NewC.getSExtValue())) {
+            isLegalICmpImmediate(NewC.getSExtValue()) &&
+            ShiftBits <= TLI.getShiftAmountThreshold(ShValTy)) {
           auto &DL = DAG.getDataLayout();
-          EVT ShiftTy = getShiftAmountTy(N0.getValueType(), DL,
+          EVT ShiftTy = getShiftAmountTy(ShValTy, DL,
                                          !DCI.isBeforeLegalize());
-          EVT CmpTy = N0.getValueType();
+          EVT CmpTy = ShValTy;
           SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
                                       DAG.getConstant(ShiftBits, dl, ShiftTy));
           SDValue CmpRHS = DAG.getConstant(NewC, dl, CmpTy);


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